Abstract: A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge that allocates use of the at least one device between the first processor and the second processor.

Abstract: An improved method and apparatus for time stamping events occurring on a large scale distributed network uses a local counter associated with each processor of the distributed network. Each counter resets at the same time globally so that all events are recorded with respect to a particular time. The counter is stopped when a critical event is detected. The events are masked or filtered in an online or offline fashion to eliminate non-critical events from triggering a collection by the system monitor or service/host processor. The masking can be done dynamically through the use of an event history logger. The central system may poll the remote processor periodically to receive the accurate counter value from the local counter and device control register. Remedial action can be taken when conditional probability calculations performed on the historical information indicate that a critical event is about to occur.

Abstract: A novel massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. Novel use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Abstract: Method and apparatus of prefetching streams of varying prefetch depth dynamically changes the depth of prefetching so that the number of multiple streams as well as the hit rate of a single stream are optimized. The method and apparatus in one aspect monitor a plurality of load requests from a processing unit for data in a prefetch buffer, determine an access pattern associated with the plurality of load requests and adjust a prefetch depth according to the access pattern.

Abstract: A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Abstract: System including a processor card containing at least two processors, and a memory card containing at least two memory units. At least one memory unit is associated with each processor. A controller dynamically allocates memory in the at least two memory units to the at least two processors.

Abstract: A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge that allocates use of the at least one device between the first processor and the second processor.

Abstract: A method and structure for an emulation system comprises of a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system, a plurality of cache directories, each connected to one of the arrays, and a plurality of global coherence directories, each connected to one of the arrays. Each of the global coherence directories maintain information on all memory lines remotely cached by each of the cache directories.

Abstract: An improved method and apparatus for time stamping events occurring on a large scale distributed network uses a local counter associated with each processor of the distributed network. Each counter resets at the same time globally so that all events are recorded with respect to a particular time. The counter is stopped when a critical event is detected. The events are masked or filtered in an online or offline fashion to eliminate non-critical events from triggering a collection by the system monitor or service/host processor. The masking can be done dynamically through the use of an event history logger. The central system may poll the remote processor periodically to receive the accurate counter value from the local counter and device control register. Remedial action can be taken when conditional probability calculations performed on the historical information indicate that a critical event is about to occur.

Abstract: A method and structure for a “dynamic CCR/sparse directory implementation,” includes maintaining state information of the main memory cached in the shared caches of the other compute nodes, organizing a cache directory so that the state information can be stored in a first area efficient CCR directory format, switching to a second sparse directory format if the entry is shared by more than one other compute node, and dynamically switching between formats so as to maximize the number of entries stored in the directory.

Abstract: A method and structure for an emulation system comprises of a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system, a plurality of cache directories, each connected to one of the arrays, and a plurality of global coherence directories, each connected to one of the arrays. Each of the global coherence directories maintain information on all memory lines remotely cached by each of the cache directories.

Abstract: A method and structure for a “dynamic CCR/sparse directory implementation,” includes maintaining state information of the main memory cached in the shared caches of the other compute nodes, organizing a cache directory so that the state information can be stored in a first area efficient CCR directory format, switching to a second sparse directory format if the entry is shared by more than one other compute node, and dynamically switching between formats so as to maximize the number of entries stored in the directory.