Patents by Inventor Krishnaraj S. Rao
Krishnaraj S. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140129742Abstract: A technique for controlling (e.g. (re)setting, adjusting, fixing, increasing, decreasing, determining, monitoring, calculating, measuring, storing) a holding time of a request from a controller of a host device to an endpoint of a peripheral device across a universal serial bus reduces power and memory loss and enhances overall system performance. The host device may include a programmable and/or hardwired controller for controlling the amount of time before the request from the host device is initially sent and/or resent to the endpoint of the peripheral device across the universal serial bus.Type: ApplicationFiled: November 8, 2012Publication date: May 8, 2014Applicant: NVIDIA CORPORATIONInventors: Chung-Hong Lai, Krishnaraj S. Rao, Rahul Jain
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Patent number: 8700808Abstract: A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.Type: GrantFiled: December 28, 2007Date of Patent: April 15, 2014Assignee: NVIDIA CorporationInventors: Radoslav Danilak, Krishnaraj S. Rao
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Patent number: 8694688Abstract: A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.Type: GrantFiled: December 28, 2007Date of Patent: April 8, 2014Assignee: NVIDIA CorporationInventors: Radoslav Danilak, Krishnaraj S. Rao
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Patent number: 8595394Abstract: A method for dynamic buffering of disk I/O command chains for a computer system. The method includes receiving a plurality of disk I/O command chains from at least one thread executing on a processor of the computer system. A respective plurality of pointers for the disk I/O command chains are stored in a buffer of a disk controller. The disk I/O command chains are accessed for execution by the disk controller by serially accessing the pointers in the buffer.Type: GrantFiled: December 1, 2003Date of Patent: November 26, 2013Assignee: Nvidia CorporationInventors: Radoslav Danilak, Krishnaraj S. Rao
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Patent number: 8386648Abstract: A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.Type: GrantFiled: December 1, 2003Date of Patent: February 26, 2013Assignee: Nvidia CorporationInventors: Radoslav Danilak, Krishnaraj S. Rao
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Patent number: 7746349Abstract: To display a row of characters in the VGA alphanumeric mode, the ASCII and attribute bits for all such characters are retrieved from the main memory and stored in a local cache memory. The font and unused bits that are also retrieved from the memory during the retrieval of ASCII and attribute bits are discarded. The stored ASCII and attribute bits for each such character is then used to compute the address of the associated font bits in the main memory. Next, for each character, the font bits are retrieved from the main memory using a burst read operation and using the computed address for that font. The font bits associated with all the characters in the row are stored in the local cache memory and are subsequently scanned out to be used in the display of the characters.Type: GrantFiled: March 16, 2005Date of Patent: June 29, 2010Assignee: NVIDIA CorporationInventors: Krishnaraj S. Rao, David G. Reed, Sean Jeffrey Treichler
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Patent number: 7633461Abstract: The graphics display system comprises a plurality of heads. Each of the heads includes a VGA controller and each of the heads is adapted for a display. The display system also includes a host coupled to the heads, wherein all the standard VGA settings for each of the heads could be programmed by a single command by the host. A method and system in accordance with the invention includes one VGA controller per head. In a broadcast mode a write transaction from the bus is broadcast to both heads. The output timing registers specific to a non-CRT output are not broadcast. To provide broadcast VGA to a CRT and/or a flat panel, software sets up the timing in extended registers and enables the display devices. The VGA application can provide mode settings via the appropriate write VGA registers and the correct display will be on each head.Type: GrantFiled: April 21, 2006Date of Patent: December 15, 2009Assignee: NVIDIA CorporationInventors: Jonah Matthew Alben, Krishnaraj S. Rao
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Publication number: 20080177925Abstract: A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.Type: ApplicationFiled: December 28, 2007Publication date: July 24, 2008Inventors: Radoslav Danilak, Krishnaraj S. Rao
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Publication number: 20080177914Abstract: A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.Type: ApplicationFiled: December 28, 2007Publication date: July 24, 2008Inventors: Radoslav Danilak, Krishnaraj S. Rao
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Patent number: 7301542Abstract: A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.Type: GrantFiled: September 29, 2004Date of Patent: November 27, 2007Assignee: NVIDIA CorporationInventors: Michael Toksvig, Walter Donovan, Jonah M. Alben, Krishnaraj S. Rao, Stephen D. Lew
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Patent number: 7095386Abstract: A graphics display system is disclosed. The display system comprises a plurality of heads. Each of the plurality of heads includes a VGA controller and each of the plurality of heads is adapted for a display. The graphics display system also includes a host coupled to the plurality of heads, wherein all the standard VGA settings for each of the plurality of the heads could be programmed by a single command by the host. Each of the heads are adapted for a display. A system and method for providing a broadcast mode VGA feature is disclosed. A method and system in accordance with the present invention includes one VGA controller per head. In so doing, in a broadcast mode a write transaction from the bus is broadcast or written to both heads. Also, in a broadcast mode, the VGA read data from the bus always comes from one of the heads. The output timing registers specific to a non-CRT output are not broadcast.Type: GrantFiled: June 7, 2001Date of Patent: August 22, 2006Assignee: nVidia CorporationInventors: Jonah Matthew Alben, Krishnaraj S. Rao
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Patent number: 7081896Abstract: Methods and apparatus for changing the timing of memory requests in a graphics system. Reading data from memory in a graphics system causes ground bounce and other electrical noise. The resulting ground bounce may be undesirably synchronized with a video retrace signal sent to a display, and may therefore cause visible artifacts. Embodiments of the present invention shift requests made by one or more clients by a duration or durations that vary with time, thereby changing the timing of the data reads from memory. The requests may be shifted by a different duration for each memory request, for each frame, or multiples of requests or frames. The durations may be random, pseudo-random, or determined by another algorithm, and they may advance or delay the requests. By making the ground bounce and other noise asynchronous with the video retrace signal, these artifacts are reduced or eliminated.Type: GrantFiled: September 3, 2002Date of Patent: July 25, 2006Assignee: NVIDIA CorporationInventors: Krishnaraj S. Rao, David G. Reed, Jeff Irwin
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Patent number: 6870542Abstract: A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.Type: GrantFiled: June 28, 2002Date of Patent: March 22, 2005Assignee: NVIDIA CorporationInventors: Michael Toksvig, Walter Donovan, Jonah M. Alben, Krishnaraj S. Rao, Stephen D. Lew
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Publication number: 20040001067Abstract: A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Applicant: NVIDIA CorporationInventors: Michael Toksvig, Walter Donovan, Jonah M. Alben, Krishnaraj S. Rao, Stephen D. Lew
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Publication number: 20020186218Abstract: A graphics display system is disclosed. The display system comprises a plurality of heads. Each of the plurality of heads includes a VGA controller and each of the plurality of heads is adapted for a display. The graphics display system also includes a host coupled to the plurality of heads, wherein all the standard VGA settings for each of the plurality of the heads could be programmed by a single command by the host. Each of the heads are adapted for a display. A system and method for providing a broadcast mode VGA feature is disclosed. A method and system in accordance with the present invention includes one VGA controller per head. In so doing, in a broadcast mode a write transaction from the bus is broadcast or written to both heads. Also, in a broadcast mode, the VGA read data from the bus always comes from one of the heads. The output timing registers specific to a non-CRT output are not broadcast.Type: ApplicationFiled: June 7, 2001Publication date: December 12, 2002Inventors: Jonah Matthew Alben, Krishnaraj S. Rao