Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.

Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.

Abstract: Certain aspects of the present disclosure are directed to a circuit for switch control. The circuit generally includes a plurality of flip-flops, each of the plurality of flip-flops having an input coupled to a respective one of a plurality of enable signals, a NOR gate having inputs coupled to outputs of the plurality of flip-flops; a plurality of AND gates, each having an input coupled to a respective one of the plurality of enable signals and having another input coupled to an output of the NOR gate, and a delay element coupled between the output of the NOR gate and reset inputs of the plurality of flip-flops.

Abstract: Certain aspects of the present disclosure are directed to a circuit for switch control. The circuit generally includes a plurality of flip-flops, each of the plurality of flip-flops having an input coupled to a respective one of a plurality of enable signals, a NOR gate having inputs coupled to outputs of the plurality of flip-flops; a plurality of AND gates, each having an input coupled to a respective one of the plurality of enable signals and having another input coupled to an output of the NOR gate, and a delay element coupled between the output of the NOR gate and reset inputs of the plurality of flip-flops.

Abstract: A device has a first switch in a first transmit path coupled between an output of a first DAC (digital-to-analog converter) in the first transmit path and an input of a first baseband filter in the first transmit path. The device also includes a second switch coupled between the output of the first DAC and an input of a second baseband filter in a second transmit path. The second switch is permanently open. The device also has a third switch and a fourth switch. The third switch is coupled between an output of a second DAC in the second transmit path and the input of the second baseband filter. The fourth switch is coupled between the output of the second DAC and the input of the first baseband filter.

Abstract: In certain aspects, an apparatus includes a plurality of phase generators configured to generate a first plurality of local oscillator (LO) phase signals, wherein the plurality of phase generators includes a first set of phase generators and a second set of phase generators. The apparatus also includes a duty cycle generator coupled to the plurality of phase generators, wherein the duty cycle generator is configured to receive the first plurality of LO phase signals and to generate a second plurality of LO phase signals by converting a duty cycle of each of the first plurality of LO phase signals. The first set of phase generators is located adjacent to a first side of the duty cycle generator and the second set of phase generators is located adjacent to a second side of the duty cycle generator, the second side being opposite the first side.

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.

Abstract: An apparatus is disclosed for mixer biasing with baseband filter common-mode voltage. In an example aspect, the apparatus includes a mixer, a baseband filter, and a bias circuit. The mixer has a mixer transistor that is coupled to a bias node and a baseband node. The baseband filter is coupled to the mixer via the baseband node. The baseband filter is configured to operate with a common-mode reference voltage that is associated with a common-mode voltage applied at the baseband node. The bias circuit is coupled to the baseband filter and the bias node. The bias circuit is configured to receive the common-mode reference voltage from the baseband filter and generate, at the bias node, a bias voltage for biasing the mixer transistor based on the common-mode reference voltage.

Abstract: An apparatus is disclosed for mixer biasing with baseband filter common-mode voltage. In an example aspect, the apparatus includes a mixer, a baseband filter, and a bias circuit. The mixer has a mixer transistor that is coupled to a bias node and a baseband node. The baseband filter is coupled to the mixer via the baseband node. The baseband filter is configured to operate with a common-mode reference voltage that is associated with a common-mode voltage applied at the baseband node. The bias circuit is coupled to the baseband filter and the bias node. The bias circuit is configured to receive the common-mode reference voltage from the baseband filter and generate, at the bias node, a bias voltage for biasing the mixer transistor based on the common-mode reference voltage.

Abstract: A communication circuit may include mixers configured to generate voltage mode outputs. The communication circuit may further include voltage nodes configured to sum the voltage mode outputs produced by the mixers to generate intermediate voltage mode signals. The communication circuit may further include transconductors configured to convert the intermediate voltage mode signals to intermediate current mode signals. The communication circuit may further include at least one current node configured to sum the intermediate current mode signals to generate at least one mixer output signal.

Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.

Abstract: A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit for shifting a first logic domain to a second logic domain. In particular, the level shifting circuit can receive an input signal having a first logic domain with a first high voltage and a first low voltage. The level shifting circuit can receive inputs corresponding to a second high voltage and a second low voltage from the second logic domain. The level shifting circuit can concurrently switch the first high voltage and first low voltage at the input to the second high voltage and the second low voltage to produce a level-shifted version of the input signal at the output. The level shifting circuit can also have a plurality of guard transistors that prevent overvoltage of the circuit components.

Abstract: A circuit includes a first amplifier path comprising a first amplifier, MA, a second amplifier path comprising a cascode device and a second amplifier, MB, a node defined by a source of the cascode device and a drain of the second amplifier, MB, and a capacitance coupled between the node and a source of the second amplifier, MB.

Abstract: A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit for shifting a first logic domain to a second logic domain. In particular, the level shifting circuit can receive an input signal having a first logic domain with a first high voltage and a first low voltage. The level shifting circuit can receive inputs corresponding to a second high voltage and a second low voltage from the second logic domain. The level shifting circuit can concurrently switch the first high voltage and first low voltage at the input to the second high voltage and the second low voltage to produce a level-shifted version of the input signal at the output. The level shifting circuit can also have a plurality of guard transistors that prevent overvoltage of the circuit components.

Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.

Abstract: A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase.

Abstract: A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase.