Patents by Inventor Krishnaswamy Viswanathan

Krishnaswamy Viswanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10761586
    Abstract: Systems, apparatuses and methods may provide for technology that determines a first real-time correlation between a power consumption of a processor and an operating frequency of the processor, determines a second real-time correlation between a performance level of the processor and the operating frequency of the processor, and sets the operating frequency of the processor to a value based on the first and second real-time correlations. In one example, the performance level or performance per watt of the processor decreases at one or more operating frequencies greater than the value.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Keqiang Wu, Yong-fong Lee, Krishnaswamy Viswanathan, Emad Guirguis
  • Publication number: 20190041943
    Abstract: Systems, apparatuses and methods may provide for technology that determines a first real-time correlation between a power consumption of a processor and an operating frequency of the processor, determines a second real-time correlation between a performance level of the processor and the operating frequency of the processor, and sets the operating frequency of the processor to a value based on the first and second real-time correlations. In one example, the performance level or performance per watt of the processor decreases at one or more operating frequencies greater than the value.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 7, 2019
    Inventors: Keqiang Wu, Yong-fong Lee, Krishnaswamy Viswanathan, Emad Guirguis
  • Publication number: 20190034337
    Abstract: A method is described. The method includes recognizing higher priority users of a multi-level system memory characterized by a faster higher level and a slower lower level in which the higher level is to act as a cache for the lower level and in which a first capacity of the higher level is less than a second capacity of the lower level such that caching resources of the higher level are oversubscribe-able. The method also includes performing at least one of: declaring an amount of the second capacity un-useable to reduce oversubscription of the caching resources; allocating system memory address space of the multi-level system memory so that requests associated with lower priority users will not compete with requests associated with the higher priority users for the caching resources.
    Type: Application
    Filed: December 28, 2017
    Publication date: January 31, 2019
    Inventors: Mohamed ARAFA, Krishnaswamy VISWANATHAN
  • Publication number: 20180241811
    Abstract: Disclosed is a mechanism for determining incompatible co-tenants in a cloud network. Cloud performance data is received indicating resource usage of tenants operating on a per server basis. Cross-correlation analysis is performed on past resource usage for each tenant pair operating on the server to determine correlated tenant pairs. Time series forecasting of predicted resource usage is performed for each tenant in the correlated tenant pairs. Cross-correlation analysis is then performed on the predicted resource usage for each correlated tenant pair to determine incompatible co-tenant pairs. The determined incompatible co-tenant pairs may be forwarded toward an orchestration system for hardware resource allocation in the cloud network.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 23, 2018
    Applicant: Intel Corporation
    Inventors: Li Chen, Krishnaswamy Viswanathan, Khun Ban
  • Patent number: 9524219
    Abstract: Durable atomic transactions for non-volatile media are described. A processor includes an interface to a non-volatile storage medium and a functional unit to perform instructions associated with an atomic transaction. The instructions are to update data at a set of addresses in the non-volatile storage medium atomically. The functional unit is operable to perform a first instruction to create the atomic transaction that declares a size of the data to be updated atomically. The functional unit is also operable to perform a second instruction to start execution of the atomic transaction. The functional unit is further operable to perform a third instruction to commit the atomic transaction to the set of addresses in the non-volatile storage medium, wherein the updated data is not visible to other functional units of the processing device until the atomic transaction is complete.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Robert Bahnsen, Sridharan Sakthivelu, Vikram A. Saletore, Krishnaswamy Viswanathan, Matthew E. Tolentino, Kanivenahalli Govindaraju, Vincent J. Zimmer
  • Publication number: 20150095600
    Abstract: Durable atomic transactions for non-volatile media are described. A processor includes an interface to a non-volatile storage medium and a functional unit to perform instructions associated with an atomic transaction. The instructions are to update data at a set of addresses in the non-volatile storage medium atomically. The functional unit is operable to perform a first instruction to create the atomic transaction that declares a size of the data to be updated atomically. The functional unit is also operable to perform a second instruction to start execution of the atomic transaction. The functional unit is further operable to perform a third instruction to commit the atomic transaction to the set of addresses in the non-volatile storage medium, wherein the updated data is not visible to other functional units of the processing device until the atomic transaction is complete.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Robert Bahnsen, Sridharan Sakthivelu, Vikram A. Saletore, Krishnaswamy Viswanathan, Matthew E. Tolentino, Kanivenahalli Govindaraju, Vincent J. Zimmer
  • Publication number: 20130262779
    Abstract: Profiling and analyzing modules may be combined with hardware modules to identify a likelihood that a particular region of code in a computer program contains data that would benefit from prefetching. Those regions of code that would not benefit from prefetching may also be identified. Once a region of code has been identified, a hardware prefetcher may be selectively enabled or disable when executing code in identified code region. In some instances, once a processing device finishes executing code in the identified code region, the state of the hardware prefetcher may then be switched back to its original state. Systems, methods, and media are provided.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Jayaram BOBBA, Ryan CARLSON, Jeffrey Cook, Abhinav DAS, Jason HORIHAN, Wei LI, Suresh SRINIVAS, Sreenivas SUBRAMONEY, Krishnaswamy VISWANATHAN
  • Patent number: 5796724
    Abstract: A communications system having a first data subsystem; a data transmission controller coupled to the first data subsystem; a data line coupled to the data transmission controller having a bandwidth with a first portion and a second portion; and, a second data subsystem coupled to the data transmission controller. A method for dynamically estimating and allocating the bandwidth between the first data subsystem and the second data subsystem having the steps of measuring a utilization level of the first portion of the bandwidth by a first application; detecting whether the utilization level is outside of a predetermined range; and, changing an allocation of the first portion and the second portion of the bandwidth.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: August 18, 1998
    Assignee: Intel Corporation
    Inventors: Krishnan Rajamani, Krishnaswamy Viswanathan