Patents by Inventor Kristan Jon Monsen

Kristan Jon Monsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic display reduced blanking duration systems and methods
    Patent number: 10983583
    Abstract: The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 20, 2021
    Assignee: Apple Inc.
    Inventors: Peter F. Holland, Christopher P. Tann, Malcolm D. Gray, Hari Ganesh R. Thirunageswaram, Kristan Jon Monsen
  • ELECTRONIC DISPLAY REDUCED BLANKING DURATION SYSTEMS AND METHODS
    Publication number: 20200064902
    Abstract: The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).
    Type: Application
    Filed: August 23, 2018
    Publication date: February 27, 2020
    Inventors: Peter F. Holland, Christopher P. Tann, Malcolm D. Gray, Hari Ganesh R. Thirunageswaram, Kristan Jon Monsen