Abstract: A micro-fluid ejecting head for use in a micro-fluid ejecting apparatus includes a plurality of micro-fluid ejection devices, a plurality of driver devices for driving the plurality of micro-fluid ejection devices, and a nonvolatile programmable memory matrix. The memory matrix contains embedded programmable memory devices for storing information related to operation of the micro-fluid ejecting head. The memory matrix is configured to communicate with a controller which is external of the micro-fluid ejecting head. The information stored in the memory matrix may include identification information for the micro-fluid ejecting head, alignment characteristics of the micro-fluid ejecting head, information regarding properties of fluid used by the micro-fluid ejecting head, fluid level information, and fluid use information. The external controller accesses the information stored in the memory matrix and controls the plurality of driver devices based on the information accessed from the memory matrix.

Abstract: An inkjet printhead. The inkjet printhead includes a temperature-sensing resistor with a low voltage end which is connected to a ground structure that at least partially encloses the temperature sensing resistor.

Abstract: A method of error detection in an inkjet printing apparatus having a host coupled to a print head. The method comprises the acts of communicating a first data stream between the host and the print head, inserting a reference data stream into the first data stream, and validating the first data stream based on the reference data stream.

Abstract: A micro-fluid ejecting device includes a semiconductor substrate, a plurality of fluid ejection elements formed on the semiconductor substrate, and a plurality of nonvolatile programmable memory devices for storing information related to the operation of the micro-fluid ejecting device. The programmable memory devices, which are at least partially embedded in the semiconductor substrate, each include a source region and a drain region formed in the semiconductor substrate. The source and drain regions have a conductivity type which is opposite the conductivity type of the semiconductor substrate. An insulative layer is formed on the semiconductor substrate over the source region and drain region. A floating gate region is formed on the insulative layer and is spatially disposed between the source region and drain region. The floating gate region is electrically insulated from the source and drain regions by the insulative layer. Electrical contacts are connected to the source region and the drain region.

Abstract: Test circuits on heater chips for testing a heater circuit having a heater element and a first power device. The test circuit can include a second power device, a test device configured to hold the first power device off and the second power device on for a selected heater circuit when the test device receives a signal to activate the test circuit, and a common test output to transmit a signal indicative of a state of the selected heater circuit. Methods for using the same are also provided.

Abstract: A heater chip that includes a circuit element, and a bus that can be used to power the circuit element. The heater chip also includes a feedback circuit that is coupled to the power bus. Particularly, the feedback circuit can be configured to indicate if the bus is powered the circuit element.

Abstract: A semiconductor substrate for a micro-fluid ejection device. The substrate includes plurality of micro-fluid ejection actuators disposed adjacent a fluid supply slot in the semiconductor substrate. A plurality of power transistors, occupying a power transistor active area of the substrate, are disposed adjacent the ejection actuators and are connected through a first metal conductor layer to the ejection actuators. An array of logic circuits, occupying a logic circuit area of the substrate, is disposed adjacent the plurality of power transistors and is connected through a polysilicon conductor layer to the power transistors. A power conductor and a ground conductor for the ejection actuators is routed in a second metal conductor layer. The power conductor overlaps at least a portion of the power transistor active area of the substrate and the ground conductor overlaps at least a portion of the logic circuit area of the substrate.

Abstract: A semiconductor substrate for a micro-fluid ejecting device. The semiconductor substrate includes a plurality of fluid ejection devices disposed on the substrate. A plurality of driver transistors are disposed on the substrate for driving the plurality of fluid ejection devices. A programmable memory matrix containing embedded programmable memory devices is operatively connected to the micro-fluid ejecting device for collecting and storing information on the semiconductor substrate for operation of the micro-fluid ejecting device. The programmable memory matrix provides a high density of memory bits embedded on the substrate for storing information about the micro-fluid ejecting device.

Abstract: An integrated circuit having a plurality of devices. The plurality of devices have a plurality of device characteristics. A sectional cut through the integrated circuit reveals the plurality of device characteristics.

Abstract: A semiconductor substrate for a micro-fluid ejection device. The substrate includes plurality of micro-fluid ejection actuators disposed adjacent a fluid supply slot in the semiconductor substrate. A plurality of power transistors, occupying a power transistor active area of the substrate, are disposed adjacent the ejection actuators and are connected through a first metal conductor layer to the ejection actuators. An array of logic circuits, occupying a logic circuit area of the substrate, is disposed adjacent the plurality of power transistors and is connected through a polysilicon conductor layer to the power transistors. A power conductor and a ground conductor for the ejection actuators is routed in a second metal conductor layer. The power conductor overlaps at least a portion of the power transistor active area of the substrate and the ground conductor overlaps at least a portion of the logic circuit area of the substrate.

Abstract: Test circuits on heater chips for testing a heater circuit having a heater element and a first power device. The test circuit can include a second power device, a test device configured to hold the first power device off and the second power device on for a selected heater circuit when the test device receives a signal to activate the test circuit, and a common test output to transmit a signal indicative of a state of the selected heater circuit. Methods for using the same are also provided.

Abstract: Some embodiments of the present invention provide an inkjet print head having a housing defining an ink reservoir, a nozzle portion including a nozzle plate defining an ink chamber in fluid communication with the ink reservoir, and forming a fluid flow path between the ink chamber and the ink reservoir, and a substrate coupled to the nozzle plate and having a surface substantially positioned over the nozzle plate. At least one heating element can be coupled to the substrate, and can be positioned adjacent the surface to heat a portion of the ink chamber. In some embodiments, the inkjet print head comprises a control circuit coupled to the at least one heating element for controlling the heating element, and a temperature sense element positioned substantially between the at least one heating element and the control circuit or in at least partially overlapping relationship with the heating element.

Abstract: An inkjet print head chip having MOS logic blocks that also includes temperature sense resistors implanted in the chip. These resistors are preferably made of N-Well material.

Abstract: An improved heater chip for an ink jet print head, the chip including an active heater array and an inactive heater array located adjacent to and extending away from the end of the active heater array. The inactive heater array provides a region adjacent the end of the active heater array that is substantially planar, and also provides a plurality of current paths which reduces energy differences between heater resistors adjacent the end of the active heater array and other heater resistors in the heater array.

Abstract: Power is provided from one portion of a printer, such as a printer electronics module, to another portion of the printer, such as a printhead. Logic signals produced in a first electronic module of the printer are transmitted to a second electronics module of the printer. A power signal is derived from the logic signals without interfering with the magnitude or duration of logic signals, and the logic power signal is applied to power the second electronic module without having a separate dedicated power line.

Abstract: A semiconductor substrate for a microfluid ejection head. The substrate includes a plurality of fluid ejection actuators disposed on the substrate. A plurality of driver transistors are disposed on the substrate for driving the plurality of fluid ejection actuators. Each of the driver transistors have an active area ranging from about 1000 to less than about 15,000 ?m2. A plurality of logic circuits including at least one logic transistor are coupled to the driver transistors. The driver and logic transistors are provided by a high density array of MOS transistors wherein at least the logic transistors have a gate length of from about 0.1 to less than about 3 microns.