Abstract: A receiving modem is locked to a transmitting modem by employing a burst data and clock signal having an effective data rate compatible with the data rate of a receiving data set. The receive modem processes a transmitted analog signal as sent by the transmitting modem to provide a digital signal which is applied to an interpolation filter. The filter provides at an output a retimed signal. This retimed signal is monitored by a baud sync measurement circuit which detects the drift of baud transitions in the retimed interpolated signal to provide an output phase error signal. This phase error signal is used to control the filter coefficients of the interpolation filter for the next data block. In this manner the interpolation filter provides a newly retimed digital output signal according to the detected phase error. The output signal is demodulated and converted to a burst data and a burst clock signal for application to a receiving data set.

Abstract: There is disclosed a multiple processor system which employs dynamically programmable processing elements (DDPE) utilized as slave devices and under the control of a master processor. A plurality of DPPE's have input/output data lines connected to a digital signal processing (DSP) bus. Communication between the DPPE's is afforded via the (DSP) bus from a master processor which interfaces with the bus via a dual port memory designated as a global memory. Each DPPE is connected together via another bidirectional serial bus so that the individual DPPE's can communicate one with the other in regard to processing and exchanging of arithmetic data. The digital signal processing bus allows the master processor to interface with the DPPE devices for control of input/output and control functions. In this manner, the master processor interfaces directly with a codec and has outputs which allow the transmission of plaintext or ciphertext data which data is formed by arithmetic operations performed by the slave DPPE's.

Abstract: A dynamically programmable processing element (DPPE) is disclosed which element has the utility in a digital processing system which requires complicated arithmetic procedures to be implemented. The DPPE device is a special purpose computer which essentially has a program bus for transmitting and receiving program data from an external source. A data bus is also provided which bus can transmit or receive digital data. Coupled between the buses are input and output registers or buffers which are capable of storing transmitted or received data propagating on either of said buses. A program memory has an input coupled to said program bus and means coupling the output of the program memory to the program bus. A data memory has an addressable input means coupled to the program bus and an output coupled to the data bus.