Patents by Inventor Kritika Aditya

Kritika Aditya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bit-line repeater insertion architecture
    Patent number: 10891992
    Abstract: An SRAM architecture to optimize the performance of the SRAM. The local bit-lines are activated one at a time with control signals from a decoder. The global bit-lines are broken with repeaters to optimize performance. This guarantees optimal performance for the SRAM array across a wide range of supply voltages spanning from the nominal voltage of a process to a sub-threshold range.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: January 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Prashant Dubey, Jamil Kawa, Kritika Aditya
  • Reset before write architecture and method
    Patent number: 10867665
    Abstract: An SRAM bit-cell with independent write and read ports and an architecture utilizing a feedback loop from the read port to the write port of half-selected bit-cells. This guarantees absolute data retention of all SRAM bit-cells not fully selected for write operation across a wide range of supply voltage spanning from the nominal voltage of a process to a sub-threshold range.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: December 15, 2020
    Assignee: Synopsys, Inc.
    Inventors: Prashant Dubey, Jamil Kawa, Kritika Aditya