Abstract: The present invention relates to a computer system having a sequence controller for allowing direct memory access devices to access peripheral devices. The sequence controller allows the peripheral devices access to a global bus by providing access in a round-robin fashion. A microprocessor associated with the sequence controller and direct memory access has access to the global bus after each direct memory access. The amount of data allowed to be transferred in each direct memory access is restricted so that each device is equally serviced.

Abstract: In a computer system having at least a bus with at least one central processing unit (CPU), one random access memory (RAM), and a first configuration of a plurality of different types of peripheral units (e.g. tape drives, disk drives, diskette drives, printers, unit record peripherals, etc.) coupled to the bus, an apparatus for controlling the first configuration and also capable of controlling a predetermined number of other configurations of different types of peripheral units when any of that predetermined number of configurations of peripheral units is coupled to the bus.

Abstract: A priority determination technique for use in a data processing system having a data processor coupled with a plurality of peripheral interface logic elements or boxes for transferring data to such boxes serially by bit, such interface boxes coupled along a daisy chained serial data transfer bus. Each of such boxes is coupled to interface with one or more peripherals for transferring data with the bus. Each interface box includes a priority network including a shift register for receiving bits of the data, wherein a mark bit is initially shifted through the shift register prior to the shifting of the data therein. The interface box address is compared with the respective stages of the shift register and generates a priority signal when the stage containing the mark bit compares with the box address. The priority signal is utilized to provide such highest priority interrupt requesting interface device with sole access for the next data transfer wth the processor.