Patents by Inventor Kshitij A. Doshi

Kshitij A. Doshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11797690
    Abstract: Examples herein relate to an interface selectively providing access to a memory region for a work request from an entity by providing selective access to a physical address of the memory region and selective access to a cryptographic key for use by a memory controller to access the memory region. In some examples, providing selective access to a physical address conversion is based on one or more of: validation of a certificate received with the work request and an identifier of the entity being associated with a process with access to the memory region. Access to the memory region can be specified to be one or more of: create, read, update, delete, write, or notify. A memory region can be a page or sub-page sized region. Different access rights can be associated with different sub-portions of the memory region, wherein the access rights comprise one or more of: create, read, update, delete, write, or notify.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Ned Smith, Kshitij A. Doshi, Francesc Guim Bernat, Kapil Sood, Tarun Viswanathan
  • Publication number: 20230273821
    Abstract: A method is described. The method includes dispatching jobs across electronic hardware components. The electronic hardware components are to process the jobs. The electronic hardware components are coupled to respective cooling systems. The respective cooling systems are each capable of cooling according to different cooling mechanisms. The different cooling mechanisms have different performance and cost operating realms. The dispatching of the jobs includes assigning the jobs to specific ones of the electronic hardware components to keep the cooling systems operating in one or more of the realms having lower performance and cost than another one of the realms.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 31, 2023
    Inventors: Amruta MISRA, Francesc GUIM BERNAT, Kshitij A. DOSHI, Marcos E. CARRANZA, John J. BROWNE, Arun HODIGERE
  • Publication number: 20230251915
    Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 10, 2023
    Applicant: Intel Corporation
    Inventors: Vadim Sukhomlinov, Kshitij A. Doshi
  • Patent number: 11711268
    Abstract: Methods and apparatus to execute a workload in an edge environment are disclosed. An example apparatus includes a node scheduler to accept a task from a workload scheduler, the task including a description of a workload and tokens, a workload executor to execute the workload, the node scheduler to access a result of execution of the workload and provide the result to the workload scheduler, and a controller to access the tokens and distribute at least one of the tokens to at least one provider, the provider to provide a resource to the apparatus to execute the workload.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 25, 2023
    Assignee: INTEL CORPORATION
    Inventors: Ned Smith, Francesc Guim Bernat, Sanjay Bakshi, Katalin Bartfai-Walcott, Kapil Sood, Kshitij Doshi, Robert Munoz
  • Patent number: 11710034
    Abstract: A mechanism is described for facilitating misuse index for explainable artificial intelligence in computing environments, according to one embodiment. A method of embodiments, as described herein, includes mapping training data with inference uses in a machine learning environment, where the training data is used for training a machine learning model. The method may further include detecting, based on one or more policy/parameter thresholds, one or more discrepancies between the training data and the inference uses, classifying the one or more discrepancies as one or more misuses, and creating a misuse index listing the one or more misuses.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: July 25, 2023
    Assignee: INTEL CORPORATION
    Inventors: Glen J. Anderson, Rajesh Poornachandran, Kshitij Doshi
  • Patent number: 11704424
    Abstract: An embodiment of a semiconductor apparatus may include technology to receive data with a unique identifier, and bypass encryption logic of a media controller based on the unique identifier. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Mark Schmisseur, Kshitij Doshi, Kapil Sood, Tarun Viswanathan
  • Publication number: 20230205606
    Abstract: Systems, apparatus, and methods to workload optimize hardware are disclosed herein. An example apparatus includes power control circuitry to determine an application ratio based on an instruction to be executed by one or more cores of a processor to execute a workload, and configure, before the execution of the workload, at least one of (i) the one or more cores of the processor based on the application ratio or (ii) uncore logic of the processor based on the application ratio, and execution circuitry to execute the workload with the at least one of the one or more cores or the uncore logic.
    Type: Application
    Filed: March 26, 2021
    Publication date: June 29, 2023
    Inventors: Stephen Palermo, Neelam Chandwani, Kshitij Doshi, Chetan Hiremath, Rajesh Gadiyar, Udayan Mukherjee, Daniel Towner, Valerie Parker, Shubha Bommalingaiahnapallya, Rany ElSayed
  • Publication number: 20230195835
    Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 22, 2023
    Inventors: Dmitry Y. Babokin, Kshitij A. Doshi, Vadim Sukhomlinov
  • Publication number: 20230156084
    Abstract: Methods and apparatus to adaptively manage data collection devices in distributed computing systems are disclosed. Example disclosed methods involve instructing a first data collection device to operate according to a first rule. The example first rule specifies a first operating mode and defining a first event of interest. Example disclosed methods also involve obtaining first data from the first data collection device while operating according to the first rule. Example disclosed methods also involve, in response to determining that the first event of interest has occurred based on the first data, providing a second rule based on the first data to the first data collection device, and providing a third rule to a second data collection device. The example second rule specifies a second operating mode and defines a second event of interest, and the examples third rule specifies a third operating mode.
    Type: Application
    Filed: October 21, 2022
    Publication date: May 18, 2023
    Inventors: Tao Zhong, Gang Deng, Zhongyan Lu, Kshitij Doshi
  • Patent number: 11645127
    Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Vadim Sukhomlinov, Kshitij A. Doshi
  • Publication number: 20230137191
    Abstract: An apparatus of a computing node of a computing network, a method to be performed at the apparatus, one or more computer-readable storage media storing instructions to be implemented at the apparatus, and a system including the apparatus. The apparatus includes a processing circuitry to: receive, from an orchestration block, a first workload (WL) package including a WL and first computing resource (CR) metadata; recompose the first WL package into a second WL package that includes the WL and second CR metadata that is different from the first CR metadata, is based at least in part on CR information regarding a server architecture onto which the WL is to be deployed, and is further to indicate one or more processors of the server architecture onto which the WL is to be deployed; and send the second WL package to one or more processors of the server architecture for deployment of the WL thereon.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Inventors: Adrian C. Hoban, Thijs Metsch, John J. Browne, Kshitij A. Doshi, Francesc Guim Bernat, Anand Haridass, Chris M. MacNamara, Amruta Misra, Vikrant Thigle
  • Publication number: 20230138094
    Abstract: Methods and apparatus for opportunistic memory pools. The memory architecture is extended with logic that divides and tracks the memory fragmentation in each of a plurality of smart devices in two virtual memory partitions: (1) the allocated-unused partition containing memory that is earmarked for (allocated to), but remained un-utilized by the actual workloads running, or, by the device itself (bit-streams, applications, etc.); and (2) the unallocated partition that collects unused memory ranges and pushes them in to an Opportunistic Memory Pool (OMP) which is exposed to the platform's memory controller and operating system. The two partitions of the OMP allow temporary utilization of otherwise unused memory. Under alternate configurations, the total amount of memory resources is presented as a monolithic resource or two monolithic memory resources (unallocated and allocated but unused) available for utilization by the devices and applications running in the platform.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 4, 2023
    Inventors: Francesc GUIM BERNAT, Marcos E. CARRANZA, Cesar Ignacio MARTINEZ SPESSOT, Kshitij A. DOSHI, Ned SMITH
  • Patent number: 11640305
    Abstract: Examples are described that relate to waking up or invoking a function such as a processor-executed application or a hardware device. The application or a hardware device can specify which sources can cause wake-ups and which sources are not to cause wake-ups. A device or processor-executed software can monitor reads from or writes to a region of memory and cause the application or a hardware device to wake-up unless the wake-up is specified as inhibited. The updated region of memory can be precisely specified to allow a pinpoint retrieval of updated content instead of scanning a memory range for changes. In some cases, a write to a region of memory can include various parameters that are to be used by the woken-up application or a hardware device. Parameters can include a source of a wake-up, a timer to cap execution time, or any other information.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 2, 2023
    Assignee: Intel Corporation
    Inventors: Alexander Bachmutsky, Kshitij A. Doshi, Raghu Kondapalli, Vadim Sukhomlinov
  • Patent number: 11637687
    Abstract: Methods, apparatus, systems and articles of manufacture to determine provenance for data supply chains are disclosed. Example instructions cause a machine to at least, in response to data being generated, generate a local data object and object metadata corresponding to the data; hash the local data object; generate a hash of a label of the local data object; generate a hierarchical data structure for the data including the hash of the local data object and the hash of the label of the local data object; generate a data supply chain object including the hierarchical data structure; and transmit the data and the data supply chain object to a device that requested access to the data.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 25, 2023
    Assignee: Intel Corporation
    Inventors: Ned Smith, Francesc Guim Bernat, Sanjay Bakshi, Paul O'Neill, Ben McCahill, Brian A. Keating, Adrian Hoban, Kapil Sood, Mona Vij, Nilesh Jain, Rajesh Poornachandran, Trevor Cooper, Kshitij A. Doshi, Marcin Spoczynski
  • Publication number: 20230115259
    Abstract: An apparatus for training artificial intelligence (AI) models is presented. In embodiments, the apparatus may include an input interface to receive in real time model training data from one or more sources to train one or more artificial neural networks (ANNs) associated with the one or more sources, each of the one or more sources associated with at least one of the ANNs; a load distributor coupled to the input interface to distribute in real time the model training data for the one or more ANNs to one or more AI appliances; and a resource manager coupled to the load distributor to dynamically assign one or more computing resources on ones of the AI appliances to each of the ANNs in view of amounts of the training data received in real time from the one or more sources for their associated ANNs.
    Type: Application
    Filed: July 29, 2022
    Publication date: April 13, 2023
    Inventors: Francesc GUIM BERNAT, Suraj PRABHAKARAN, Alexander BACHMUTSKY, Raghu KONDAPALLI, Kshitij A. DOSHI
  • Patent number: 11617227
    Abstract: Technologies for providing hardware resources as a service with direct resource addressability are disclosed. According to one embodiment of the present disclosure, a device receives a request to access a destination accelerator device in an edge network, the request specifying a destination address assigned to the destination accelerator device. The device determines, as a function of the destination address, a location of the destination accelerator device and sends the request to the destination accelerator device.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: March 28, 2023
    Assignee: Intel Corporation
    Inventors: Raghu Kondapalli, Alexander Bachmutsky, Francesc Guim Bernat, Ned M. Smith, Kshitij A. Doshi
  • Patent number: 11606417
    Abstract: Technologies for matching security requirements for a function-as-a-service (FaaS) function request to an edge resource having security features matching the security requirements are disclosed. According to one embodiment of the present disclosure, an edge gateway device receives, from an edge device, a request to execute an accelerated function. The edge gateway device selects, as a function of one or more security requirements requested by the edge device, an edge resource to fulfill the request. The edge gateway device transmits the request to the edge resource to fulfill the request of the edge device, according to the one or more security requirements.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: March 14, 2023
    Assignee: INTEL CORPORATION
    Inventors: Kshitij Doshi, Francesc Guim Bernat, Suraj Prabhakaran, Ned M. Smith
  • Patent number: 11604889
    Abstract: Systems, apparatuses and methods may provide for a memory apparatus that includes a client-side address space dedicated to an accessor of obfuscated multi-tenant data, wherein an executable view generation library is stored to the client-side address space. In one example, the executable view generation library is to receive a request to access at least a portion of the obfuscated multi-tenant data, convert the obfuscated multi-tenant data to deobfuscated multi-tenant data based on metadata associated with the executable view generation library and generate a single-tenant view based on the deobfuscated multi-tenant data.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Ajith K. Illendula, Kshitij A. Doshi, Vincent J. Zimmer
  • Patent number: 11586575
    Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: February 21, 2023
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Da-Ming Chiang, Kshitij A. Doshi, Suraj Prabhakaran, Mark A. Schmisseur
  • Publication number: 20230047886
    Abstract: Technologies for dynamically sharing remote resources include a computing node that sends a resource request for remote resources to a remote computing node in response to a determination that additional resources are required by the computing node. The computing node configures a mapping of a local address space of the computing node to the remote resources of the remote computing node in response to sending the resource request. In response to generating an access to the local address, the computing node identifies the remote computing node based on the local address with the mapping of the local address space to the remote resources of the remote computing node and performs a resource access operation with the remote computing node over a network fabric. The remote computing node may be identified with system address decoders of a caching agent and a host fabric interface. Other embodiments are described and claimed.
    Type: Application
    Filed: November 1, 2022
    Publication date: February 16, 2023
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan, Alejandro Duran Gonzalez, Harald Servat