Patents by Inventor Kuan-Hao SU

Kuan-Hao SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194668
    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.
    Type: Application
    Filed: February 3, 2023
    Publication date: June 13, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsuan Lin, Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20240186373
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Application
    Filed: February 7, 2024
    Publication date: June 6, 2024
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20240162218
    Abstract: An electrostatic discharge device including a gate structure, a plurality of first doped regions, and a plurality of second doped regions. The gate structure is disposed on a substrate. The gate structure includes a body part and a plurality of extension parts. The extension parts are connected with the body part, and an extension direction of the body part is different from an extension direction of the extension parts. The first doped regions are located in the substrate between the extension parts. The second doped regions are located in the substrate at two outer sides of the extension parts. The first doped regions and the second doped regions have different conductivity types.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 16, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chih Hsiang Chang, Mei-Ling Chao, Yin-Chia Tsai, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20240112959
    Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
  • Patent number: 11948973
    Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang
  • Publication number: 20240096996
    Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20240037813
    Abstract: A computer-implemented method for motion compensation of medical imaging data includes estimating, via a processor, non-periodic motion of a myocardium of a heart due to respiration and/or other body movements throughout a positron emission tomography (PET) scan based on list-mode emission data acquired during the PET scan of the heart of a subject. The method also includes performing, via the processor, event-by-event motion-corrected list-mode reconstruction on the list-mode emission data to generate cardiac images with the non-periodic motion removed.
    Type: Application
    Filed: August 1, 2022
    Publication date: February 1, 2024
    Inventors: Matthew Gilbert Spangler-Bickell, Kuan-Hao Su, Floribertus Philippus Martin Heukensfeldt Jansen, Timothy Wayne Deller
  • Patent number: 10438380
    Abstract: A medical image (24) with contrast of one imaging modality is emulated from images with other contrast characteristics. A plurality of input images (20) of a region of interest with the other contrast characteristics is received. A transform (22) which was generated by machine learning is applied to the corresponding plurality of input images (20) to generate a scalar value (38) or a vector value (38?) representing the corresponding voxel (36?) of the medical image (24) to be evaluated.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 8, 2019
    Assignees: KONINKLIJKE PHILIPS N.V., CASE WESTERN RESERVE UNIVERSITY, UNIVERSITY HOSPITALS MEDICAL GROUP, INC.
    Inventors: Lingzhi Hu, Lingxiong Shao, Raymond Frank Muzic, Kuan-Hao Su, Pengjiang Qian
  • Publication number: 20170372497
    Abstract: A medical image (24) with contrast of one imaging modality is emulated from images with other contrast characteristics. A plurality of input images (20) of a region of interest with the other contrast characteristics is received. A transform (22) which was generated by machine learning is applied to the corresponding plurality of input images (20) to generate a scalar value (38) or a vector value (38?) representing the corresponding voxel (36?) of the medical image (24) to be evaluated.
    Type: Application
    Filed: November 20, 2015
    Publication date: December 28, 2017
    Applicants: KONINKLIJKE PHILIPS N.V., CASE WESTERN RESERVE UNIVERSITY, UNIVERSITY HOSPITALS MEDICAL GROUP, INC.
    Inventors: Lingzhi HU, Lingxiong SHAO, Raymond Frank MUZIC, Kuan-Hao SU, Pengjiang QIAN