Patents by Inventor Kuan-Jui Huang
Kuan-Jui Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145298Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.Type: ApplicationFiled: February 17, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Min Huang, Tzu-Jui Wang, Jung-I Lin, Hung-Chang Chien, Kuan-Chieh Huang, Tzu-Hsuan Hsu, Chen-Jong Wang
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Publication number: 20240128216Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.Type: ApplicationFiled: January 4, 2023Publication date: April 18, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Ching-Chun Wang, Hsiao-Hui Tseng, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240096918Abstract: A device structure according to the present disclosure may include a first die having a first substrate and a first interconnect structure, a second die having a second substrate and a second interconnect structure, and a third die having a third interconnect structure and a third substrate. The first interconnect structure is bonded to the second substrate via a first plurality of bonding layers. The second interconnect structure is bonded to the third interconnect structure via a second plurality of bonding layers. The third substrate includes a plurality of photodiodes and a first transistor. The second die includes a second transistor having a source connected to a drain of the first transistor, a third transistor having a gate connected to drain of the first transistor and the source of the second transistor, and a fourth transistor having a drain connected to the source of the third transistor.Type: ApplicationFiled: January 17, 2023Publication date: March 21, 2024Inventors: Hao-Lin Yang, Tzu-Jui Wang, Wei-Cheng Hsu, Cheng-Jong Wang, Dun-Nian Yuang, Kuan-Chieh Huang
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Publication number: 20240079434Abstract: Various embodiments of the present disclosure are directed towards an image sensor including first chip and a second chip. The first chip includes a first substrate, a plurality of photodetectors disposed in the first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first bond structure disposed on the first interconnect structure. The second chip underlies the first chip. The second chip includes a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bond structure disposed on the second interconnect structure. A first bonding interface is disposed between the second bond structure and the first bond structure. The second interconnect structure is electrically coupled to the first interconnect structure by way of the first and second bond structures.Type: ApplicationFiled: January 5, 2023Publication date: March 7, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung, Yu-Chun Chen
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Publication number: 20120242623Abstract: A display device includes a display layer and a light guide plate (LGP) arranged on the display layer. A transparent plate is arranged between the LGP and the display layer, and the transparent plate houses a array of IR sensors. An IR source is arranged on the lateral surface of the LGP, and a scanning mirror is arranged on the lateral surface of the LGP. The IR sensors sense the IR light beams and determine whether a strength of the sensed IR light beams is decreased to below a predetermined threshold value, caused by a touch by a user, on the transparent plate at a location of said IR sensor, and send a signal associated with the touch to the control unit, the control unit is configured to receive the signal and determine the touch point according to the location of said IR sensor.Type: ApplicationFiled: November 20, 2011Publication date: September 27, 2012Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: HSIEN-LUNG HO, CHIU-HSIUNG LIN, KUAN-JUI HUANG
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Publication number: 20120230055Abstract: A display device includes a display layer and a light guide plate (LGP) arranged on the display layer. The LGP includes a first surface facing away from the display layer, an opposite second surface, and a lateral surface between the first and second surfaces, the lateral surface having a light incident portion. A light source and a scanning mirror are arranged on the lateral surface of the LGP. The light source configured to emit a light beam toward the scanning mirror, the scanning mirror being reciprocally rotatable about a rotating axis at a given frequency, the scanning mirror configured to reflect and direct the light beam from the light source to enter into the LGP through the light incident portion.Type: ApplicationFiled: October 11, 2011Publication date: September 13, 2012Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: HSIEN-LUNG HO, CHIU-HSIUNG LIN, KUAN-JUI HUANG
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Publication number: 20120080693Abstract: The light emitting diode package of the present invention uses photosensitive materials to form phosphor encapsulations or a phosphor layer, which can be fabricated by means of semiconductor processes in batch. Also, the concentration of phosphors in individual regions can be accurately and easily controlled by a laser printing process or by light-through holes. Accordingly, the optic effects of light emitting diode packages can be accurately adjusted.Type: ApplicationFiled: December 7, 2011Publication date: April 5, 2012Applicant: TOUCH MICRO-SYSTEM TECHNOLOGY CORPORATIONInventors: Hung-Yi LIN, Kuan-Jui HUANG, Yen-Ting KUNG, She-Fen TIEN
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Patent number: 8129206Abstract: The light emitting diode package of the present invention uses photosensitive materials to form phosphor encapsulations or a phosphor layer, which can be fabricated by means of semiconductor processes in batch. Also, the concentration of phosphors in individual regions can be accurately and easily controlled by a laser printing process or by light-through holes. Accordingly, the optic effects of light emitting diode packages can be accurately adjusted.Type: GrantFiled: June 9, 2009Date of Patent: March 6, 2012Assignee: Touch Micro-System Technology Corp.Inventors: Hung-Yi Lin, Kuan-Jui Huang, Yen-Ting Kung, She-Fen Tien
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Patent number: 7987588Abstract: The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.Type: GrantFiled: November 19, 2008Date of Patent: August 2, 2011Assignee: Touch Micro-System Technology Inc.Inventors: Kuan-Jui Huang, Chang-Ping Wang, Hsiu-Ming Li, Shih-Min Huang, Hui-Chen Kuo, Chia-Chun Chen
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Patent number: 7795131Abstract: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed.Type: GrantFiled: March 12, 2007Date of Patent: September 14, 2010Assignee: Touch Micro-System Technology Inc.Inventors: Kuan-Jui Huang, Jie-Mei Huang, Chung-Hsiang Wang
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Patent number: 7732233Abstract: The LED chip package of the present invention uses a semiconductor substrate as package substrate, which improves heat dissipation. Also, the LED chip package is incorporated with a planarization structure, which renders the LED chip and the substrate a substantially planar surface, thereby making formation of a planar patterned conductive layer possible. Accordingly, serial/parallel electrical connections between light emitting diode chips can be easily implemented by virtue of the planar patterned conductive layer.Type: GrantFiled: June 10, 2009Date of Patent: June 8, 2010Assignee: Touch Micro-System Technology Corp.Inventors: Hung-Yi Lin, Kuan-Jui Huang, Yen-Ting Kung, She-Fen Tien
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Publication number: 20100090245Abstract: The light emitting diode package of the present invention uses photosensitive materials to form phosphor encapsulations or a phosphor layer, which can be fabricated by means of semiconductor processes in batch. Also, the concentration of phosphors in individual regions can be accurately and easily controlled by a laser printing process or by light-through holes. Accordingly, the optic effects of light emitting diode packages can be accurately adjusted.Type: ApplicationFiled: June 9, 2009Publication date: April 15, 2010Inventors: Hung-Yi Lin, Kuan-Jui Huang, Yen-Ting Kung, She-Fen Tien
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Publication number: 20090273004Abstract: A chip package structure and method thereof uses a semiconductor substrate as a package substrate, which improve heat dissipation. Also, the chip package structure is incorporated with a planarization structure, which renders the chip and the package substrate a substantially planar surface, thereby making formation of a planar patterned conductive layer possible. Accordingly, electrical connections in series or in parallel between chips can be easily implemented by virtue of the planar patterned conductive layer.Type: ApplicationFiled: June 16, 2009Publication date: November 5, 2009Inventors: Hung-Yi Lin, Kuan-Jui Huang, Yen-Ting Kung, She-Fen Tien
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Publication number: 20090267108Abstract: The LED chip package of the present invention uses a semiconductor substrate as package substrate, which improves heat dissipation. Also, the LED chip package is incorporated with a planarization structure, which renders the LED chip and the substrate a substantially planar surface, thereby making formation of a planar patterned conductive layer possible. Accordingly, serial/parallel electrical connections between light emitting diode chips can be easily implemented by virtue of the planar patterned conductive layer.Type: ApplicationFiled: June 10, 2009Publication date: October 29, 2009Inventors: Hung-Yi Lin, Kuan-Jui Huang, Yen-Ting Kung, She-Fen Tien
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Publication number: 20090064496Abstract: The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.Type: ApplicationFiled: November 19, 2008Publication date: March 12, 2009Inventors: Kuan-Jui Huang, Chang-Ping Wang, Hsiu-Ming Li, Shih-Min Huang, Hui-Chen Kuo, Chia-Chun Chen
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Publication number: 20080188024Abstract: A method of fabricating micro mechanical moving member and metal interconnects thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed. After that, at least one micro mechanical moving member electrically connected to the second metal interconnect pattern is formed on the inter-metal dielectric layer by plating techniques.Type: ApplicationFiled: April 16, 2007Publication date: August 7, 2008Inventors: Kuan-Jui Huang, Hsiu-Ming Li, Shih-Min Huang, Chia-Chun Chen, Hui-Chen Kuo
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Publication number: 20080182432Abstract: The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.Type: ApplicationFiled: June 1, 2007Publication date: July 31, 2008Inventors: Kuan-Jui Huang, Chang-Ping Wang, Hsiu-Ming Li, Shih-Min Huang, Hui-Chen Kuo, Chia-Chun Chen
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Publication number: 20080146021Abstract: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed.Type: ApplicationFiled: March 12, 2007Publication date: June 19, 2008Inventors: Kuan-Jui Huang, Jie-Mei Huang, Chung-Hsiang Wang
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Patent number: 7262078Abstract: A substrate is provided. The substrate includes a plurality of devices disposed in the substrate, a plurality of contact pads disposed on a surface of the substrate and electrically connected to the devices, and a surface dielectric layer positioned on the surface of the substrate. Thereafter, a surface treatment process including at least a plasma etching process is performed. Subsequently, at least a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a dielectric layer on a surface dielectric layer. The PECVD process is performed in a high frequency/low frequency alternating manner. Following that, a masking pattern on the dielectric layer is formed, and an anisotropic etching process is carried out to form a plurality of openings corresponding to the contact pads in the dielectric layer. The openings expose the contact pads, and each opening has an outwardly-inclined sidewall.Type: GrantFiled: March 15, 2005Date of Patent: August 28, 2007Assignee: Touch Micro-System Technology Inc.Inventors: Wei-Shun Lai, Shu-Hua Hu, Kuan-Jui Huang, Chin-Chang Pan, Yuan-Chin Hsu
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Publication number: 20060263934Abstract: The chip-type micro-connector includes a package substrate, a micro-connector disposed on the package structure, a plurality of chips, and a cap layer disposed on the micro-connector and the chips. The micro-connector includes a connection substrate, a plurality of connecting wires disposed in the connection substrate, and a plurality of contact pads exposed on a surface of the connection substrate and respectively connected to each connecting wire. The chips are coupled to one another via the contact pads and the connecting wires. The cap layer packages the micro-connector and the chips on the package substrate.Type: ApplicationFiled: August 1, 2006Publication date: November 23, 2006Inventors: Shu-Hua Hu, Kuan-Jui Huang, Chin-Chang Pan