Patents by Inventor Kuan Liang Wu
Kuan Liang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8202681Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.Type: GrantFiled: July 21, 2011Date of Patent: June 19, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Lung Lin, Kuan-Liang Wu, Che-Rong Liang, Fei-Gwo Tsai
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Publication number: 20110281208Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.Type: ApplicationFiled: July 21, 2011Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng-Lung Lin, Kuan-Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
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Patent number: 8007966Abstract: A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern.Type: GrantFiled: January 14, 2011Date of Patent: August 30, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Lung Lin, Kuan Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
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Patent number: 8003281Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.Type: GrantFiled: October 13, 2008Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Feng-Lung Lin, Kuan-Liang Wu, Che-Rong Liang, Fei-Gwo Tsai
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Publication number: 20110113389Abstract: A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Lung Lin, Kuan Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
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Patent number: 7904855Abstract: Disclosed are a method and a system for partially removing circuit patterns from a multi-project wafer. This method and this system can be used to provide a multi-project-wafer to a user without disclosing proprietary circuit information of other customers. At least one integrated circuit design of a user is identified from a plurality of integrated circuit designs of a plurality of users. Those unidentified circuits can be totally removed through circuit removing method. Then the modified multi-project wafer can be delivered to the user without concerns about disclosing information of unidentified circuits which belongs to other customers. In one embodiment, a laser system may be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits. In another embodiment, a diamond-blade saw may also be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits.Type: GrantFiled: September 29, 2006Date of Patent: March 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hong Tseng, Kuan-Liang Wu
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Patent number: 7875406Abstract: A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main node and the second technology node a sub-node. A mask set including an MTM may also include single technology node masks (STMs) for mask layers in which the first technology node and second technology node and/or the patterns associated with each are not compatible. A single mask set including MTM and STMs, may be used to produce a plurality of devices, each on a different wafer.Type: GrantFiled: March 27, 2008Date of Patent: January 25, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Lung Lin, Kuan Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
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Publication number: 20100047698Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.Type: ApplicationFiled: October 13, 2008Publication date: February 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng-Lung Lin, Kuan-Liang Wu, Che-Rong Liang, Fei-Gwo Tsai
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Publication number: 20090246975Abstract: A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main node and the second technology node a sub-node. A mask set including an MTM may also include single technology node masks (STMs) for mask layers in which the first technology node and second technology node and/or the patterns associated with each are not compatible. A single mask set including MTM and STMs, may be used to produce a plurality of devices, each on a different wafer.Type: ApplicationFiled: March 27, 2008Publication date: October 1, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Lung Lin, Kuan Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
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Publication number: 20070264798Abstract: Disclosed are a method and a system for partially removing circuit patterns from a multi-project wafer. This method and this system can be used to provide a multi-project-wafer to a user without disclosing proprietary circuit information of other customers. At least one integrated circuit design of a user is identified from a plurality of integrated circuit designs of a plurality of users. Those unidentified circuits can be totally removed through circuit removing method. Then the modified multi-project wafer can be delivered to the user without concerns about disclosing information of unidentified circuits which belongs to other customers. In one embodiment, a laser system may be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits. In another embodiment, a diamond-blade saw may also be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits.Type: ApplicationFiled: September 29, 2006Publication date: November 15, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Hong Tseng, Kuan-Liang Wu
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Patent number: 7127317Abstract: The present invention provides an Intelligent Engineering Data Analysis (I-EDA) system and method to help prevent low wafer yield and prevent occurrences of abnormal events. The I-EDA has a non-conforming wafer tracing (NCWT) system that operates to correlate occurrences of abnormal events with low wafer yield. The method generally has the steps of performing a fabrication operation on wafers disposed within a wafer lot; determining if an abnormal event occurred while performing the fabrication operation on the wafers disposed within the wafer lot; using a NCWT to determine a statistical correlation between an occurrence of an abnormal event and a wafer yield of the wafers being processed during the occurrence of the abnormal event if the abnormal event occurred during processing of the wafers disposed within the wafer lot; and using the determined statistical correlation to analyze the fabrication process and thereby improve wafer yield.Type: GrantFiled: November 30, 2004Date of Patent: October 24, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen Jen Chiu, Wei-Chin Shiau, Chen Hsin Hsiung, Kuan Liang Wu, Yu-Jye Lan, Shiaw-Lin Chi, Chia Hui Hsu, Ming Tsang Yu