Patents by Inventor Kuan Lin Chen
Kuan Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990339Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.Type: GrantFiled: August 2, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
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Patent number: 11990471Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.Type: GrantFiled: August 10, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
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Publication number: 20240162227Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.Type: ApplicationFiled: November 19, 2023Publication date: May 16, 2024Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG
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Patent number: 11984488Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.Type: GrantFiled: April 30, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng
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Publication number: 20240154043Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.Type: ApplicationFiled: January 2, 2024Publication date: May 9, 2024Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240145520Abstract: The present disclosure provides a method for fabricating an image sensor. The method includes the following operations. A cavity is formed at a first surface of a substrate. A germanium layer is formed in the cavity. A first heavily doped region is formed in the germanium layer by an implantation operation. A second heavily doped region is formed at a position proximal to a top surface of the germanium layer, wherein the second heavily doped region is laterally surrounded by the first heavily doped region from a top view perspective. An interconnect structure is formed over the germanium layer.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: JHY-JYI SZE, SIN-YI JIANG, YI-SHIN CHU, YIN-KAI LIAO, HSIANG-LIN CHEN, KUAN-CHIEH HUANG, JUNG-I LIN
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Publication number: 20240144394Abstract: A Method implemented by a display system for hosting digital content team display contests and quantifying social media popularity, is implemented through a display system. The system consists of a display server and a user big data server. The method involves multiple users participating in a display team, where the display server showcases the digital content contributed by these users as showpiece. Furthermore, the display server displays the showpiece and/or the display team in a display theme and records the social media interaction behavior data of the showpiece and/or the display team, which is then transmitted to the user big data server. The user big data server calculates the social media interaction behavior data of the showpiece and/or the team based on the quality differences in social media interaction behaviors and stores them separately in a database. Users can increase the popularity and value of their created digital content by participating in the display team.Type: ApplicationFiled: September 12, 2023Publication date: May 2, 2024Inventors: Kuan Yu CHEN, You Lin YAO
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Publication number: 20240136299Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
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Publication number: 20240136401Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.Type: ApplicationFiled: January 5, 2024Publication date: April 25, 2024Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
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Publication number: 20240136484Abstract: An electronic device includes a substrate, a semiconductor unit and an insulating layer. The semiconductor unit is disposed on the substrate. The insulating layer is disposed on the semiconductor unit, and the insulating layer includes a first portion and a second portion connected to the first portion. In a top view, the first portion partially overlaps the semiconductor unit, the second portion does not overlap the semiconductor unit, and a part of an edge of the insulating layer is irregular.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicant: InnoLux CorporationInventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee, Yuan-Lin Wu
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Publication number: 20240123151Abstract: An insertion device includes an upper casing, an insertion module and a lower casing. The insertion module is disposed in the upper casing, and includes a main body assembly, an insertion seat, a first elastic member, a retraction seat and a second elastic member. When the upper casing is depressed, the insertion seat is driven by the first elastic member to perform an automatic-insertion operation, such that limiting structure between the insertion seat and the retraction seat collapses upon the collapse of another limiting structure between the insertion seat and the main body assembly, and that the retraction seat is driven by the second elastic member to perform an automatic-retraction operation.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Chen-Hao Lee, Kuan-Lin Chang
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Publication number: 20240120451Abstract: An electronic assembly is provided. The electronic assembly includes a first circuit structure including a conductive structure, a second circuit structure disposed on the first circuit structure, a plurality of electronic elements disposed on the first circuit structure, and a connecting element disposed on the first circuit layer. The connecting element is disposed between two adjacent ones of the plurality electronic elements and electrically connected to the second circuit layer and one of the two adjacent ones of the plurality of electronic elements.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Jia-Yuan CHEN, Tsung-Han TSAI, Kuan-Feng LEE, Yuan-Lin WU
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Patent number: 11952656Abstract: A physical vapor deposition (PVD) system is disclosed. The PVD system includes a pedestal configured to hold a semiconductor wafer, a cover plate configured to hold a target, and a collimator between the pedestal and the cover plate. The collimator includes a plurality of passages configured to pass source material travelling from the cover plate toward the pedestal at an angle less than a threshold angle with respect to a line perpendicular to a surface of the pedestal facing the cover plate, where the collimator is configured to block source material travelling from the cover plate toward the pedestal at an angle greater than the threshold angle, where a first passage of the plurality of passages has a first passage length, where a second passage of the plurality of passages has a second passage length, and where the first passage length is less than the second passage length.Type: GrantFiled: March 22, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lin Chen, Tsung-Yi Chou, Wei-Der Sun, Hao-Wei Kang
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Publication number: 20240105877Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
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Publication number: 20240096942Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng
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Publication number: 20240090838Abstract: A physiological signal monitoring device includes a base, a sensor, a transmitter, an adhesive layer and a pad. The sensor is carried by the base. The transmitter is coupled to the sensor. The adhesive layer is arranged on a bottom surface of the base. The pad includes an adhesive backing and a coupling backing. The adhesive backing is fabricated by weaving first threads and includes first holes. The coupling backing provides a coupling surface, and is fabricated by weaving second threads and includes second holes and piques. The piques are arranged on the coupling surface to form convex and concave three-dimensional textures on the coupling surface. The adhesive layer soaks the pad through the second holes and wraps at least one of the second threads and the first threads, so as to make the pad be connected to the base through the adhesive layer.Type: ApplicationFiled: January 18, 2023Publication date: March 21, 2024Inventors: Chieh-Hsing CHEN, Kuan-Lin CHANG
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Patent number: 11935795Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.Type: GrantFiled: July 28, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
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Patent number: 11925789Abstract: An elastic physiological patch includes a patch assembly and an implant assembly. The patch assembly includes an electronic device, and a soft patch body defining a chamber for receiving the electronic device. The implant assembly is mountable to the electronic device and includes an implant which is capable of being driven to partially pass through the patch body and which is adapted to be implanted in the skin of a subject. The implant and the patch body cooperatively seal the chamber.Type: GrantFiled: January 14, 2022Date of Patent: March 12, 2024Assignee: Bionime CorporationInventors: Chun-Mu Huang, Chieh-Hsing Chen, Jia-Nan Shen, Kuan-Lin Chang
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Patent number: 11889645Abstract: A foldable electronic device includes a first casing, a second casing, a hinge structure and a foldable display. The hinge structure connects the first casing and the second casing, and includes a plurality of supporting blocks, a plurality of first hinge blocks and a plurality of second hinge blocks. The supporting blocks are arranged side by side between the first casing and the second casing. The first hinge blocks and the second hinge blocks are respectively arranged at two sides of the supporting blocks. One of the first hinge blocks connects two of the supporting blocks adjacent to each other. One of the second hinge blocks connects two of the supporting blocks adjacent to each other. The foldable display includes a first bonding portion secured to the first casing, a second bonding portion secured to the second casing and a foldable portion aligned to the hinge structure.Type: GrantFiled: September 27, 2022Date of Patent: January 30, 2024Assignee: Acer IncorporatedInventors: Hui-Ping Sun, Wei-Chih Wang, Chun-Hung Wen, Yu-Cheng Shih, Yen-Chou Chueh, Chi-Tai Ho, Kuan-Lin Chen, Chun-Hsien Chen, Chih-Heng Tsou
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Publication number: 20230413073Abstract: Apparatus and methods are provided for determining AR filter coefficient and numbers of synchronization. In one novel aspect, the AR filter coefficient and times of synchronization are determined based on the temperatures of the oscillator. In one embodiment, the UE determines a temperature drift rate by collecting sets of temperatures before and after the UE in the sleep mode of the CDRX, generates one or more threshold look-up tables and performs an optimization selection based on the temperature drift rate and the one or more threshold of look-up tables, wherein the optimization selection comprising selecting an alpha coefficient and a number of subframes for synchronization. In another embodiment, the optimization selection is further determined based on a subcarrier spacing, and a channel type of being a static channel type and a fading channel type. The UE further performs an on-the-fly oscillator S-curve calibration based on the set of temperatures.Type: ApplicationFiled: June 17, 2023Publication date: December 21, 2023Inventors: YUAN YUAN, Jianwei Zhang, Jun Hu, Nien-En Wu, PENG YANG, Kuan-Lin Chen, Yen-Chen Chen, Cheng-Yu Tsai, Zhi Zheng