Abstract: An optical system includes an eye-tracker and a head-mounted display for providing accurate eye-tracking in interactive virtual environment. The eye-tracker includes a sensor module captures one or multiple eye images of a user. The head-mounted display includes a processor and a display for presenting the user interface. The processor provides a user interface which includes one or multiple UI elements based on one or multiple gaze points of the user which are computed based on the one or multiple eye images, acquires the distance between an estimated gaze point of the user and each UI element, acquires the score of each UI element based on the distance between the estimated gaze point and each UI element, and sets a specific UI element with a highest score as the target UI element associated with the estimated gaze point of the user.

Abstract: An optical system includes an eye-tracker and a head-mounted display for providing accurate eye-tracking in interactive virtual environment. The eye-tracker includes a sensor module captures one or multiple eye images of a user. The head-mounted display includes a processor and a display for presenting the user interface. The processor provides a user interface which includes one or multiple UI elements based on one or multiple gaze points of the user which are computed based on the one or multiple eye images, acquires the distance between an estimated gaze point of the user and each UI element, acquires the score of each UI element based on the distance between the estimated gaze point and each UI element, and sets a specific UI element with a highest score as the target UI element associated with the estimated gaze point of the user.

Abstract: During an eye-tracking operation of an optical system, one or multiple eye images are captured. One or multiple gaze points of the user are computed based on the one or multiple eye images of the user. A user interface containing one or multiple UI elements is provided based on the one or multiple gaze points of the user. A performance map of the eye-tracking operation is provided based on the one or multiple eye images of the user. At least one UI element is adjusted based on the performance map of the eye-tracking operation.

Abstract: An optical system includes an eye-tracking module and a head-mounted display. The eye-tracking module includes a first sensor module configured to capture an eye image of a user. The head-mounted display includes a processor configured to provide a user interface based on a gaze point of the user computed based on the eye image, and a display configured to present the user interface. The user interface includes a virtual FoV and at least one UI element for receiving a gaze command from the user. The at least one UI element is arranged within the FoV of the user and located outside a range of the virtual FoV of the user interface.

Abstract: In a calibration process for an eye-tracking application, a calibration mark is displayed on an instrument, and the user is instructed to keep the gaze focused on the calibration mark. Next, a dynamic image is displayed on the instrument, and the user is instructed to move his head or the instrument as indicated by the dynamic image while keeping the gaze focused on the calibration mark. The ocular information of the user is recorded during the head movement or the instrument movement for calibrating the eye-tracking application.

Abstract: An eye-tracking module includes a power management module, a sensing module and a processor. The power management module is configured to supply power according to a power control signal for operating the eye-tracking module in a corresponding mode, and provide a power status signal associated its power supplying status. The sensing module includes at least one image sensor configured to capture an eye image of a user at a sampling rate. The processor is configured to acquire eye characteristics of the user, the eye-movement information of the user, or vision information including user gaze coordinates according to the eye image. The processor is also configured to adjust the sampling rate, adjust its output frequency and/or switch the operational mode of the eye-tracking module according to the power status signal.

Abstract: An eye-tracking module includes a power management module, a sensing module and a processor. The power management module is configured to supply power according to a power control signal for operating the eye-tracking module in a corresponding mode, and provide a power status signal associated its power supplying status. The sensing module includes at least one image sensor configured to capture an eye image of a user at a sampling rate. The processor is configured to acquire eye characteristics of the user, the eye-movement information of the user, or vision information including user gaze coordinates according to the eye image. The processor is also configured to adjust the sampling rate, adjust its output frequency and/or switch the operational mode of the eye-tracking module according to the power status signal.

Abstract: In a calibration process for an eye-tracking application, a calibration mark is displayed on an instrument, and the user is instructed to keep the gaze focused on the calibration mark. Next, a dynamic image is displayed on the instrument, and the user is instructed to move his head or the instrument as indicated by the dynamic image while keeping the gaze focused on the calibration mark. The ocular information of the user is recorded during the head movement or the instrument movement for calibrating the eye-tracking application.

Abstract: A device may determine multicast information associated with participating in a multicast. The multicast information may include a virtual rendezvous (RP) address and may identify a multicast group. The device may identify a primary RP address and a secondary RP address associated with the multicast group. The primary RP address may identify a primary RP device and the secondary RP address may identify a secondary RP device. The device may identify an active RP device. The active RP device may be the primary RP device or the secondary RP device. The device may replace the virtual RP address, included in the multicast information, with information that identifies the active RP device. The information that identifies the active RP device may be the primary RP address or the secondary RP address. The device may participate in the multicast based on the information that identifies the active RP device.

Abstract: A device may determine multicast information associated with participating in a multicast. The multicast information may include a virtual rendezvous (RP) address and may identify a multicast group. The device may identify a primary RP address and a secondary RP address associated with the multicast group. The primary RP address may identify a primary RP device and the secondary RP address may identify a secondary RP device. The device may identify an active RP device. The active RP device may be the primary RP device or the secondary RP device. The device may replace the virtual RP address, included in the multicast information, with information that identifies the active RP device. The information that identifies the active RP device may be the primary RP address or the secondary RP address. The device may participate in the multicast based on the information that identifies the active RP device.

Abstract: A fabricating method of a trench-gate metal oxide semiconductor device is provided. The fabricating method includes the steps of defining a first zone and a second zone in a substrate, forming at least one first trench in the second zone, forming a dielectric layer on the first zone and the second zone, filling the dielectric layer in the first trench, performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask, forming a first gate dielectric layer on a sidewall of the second trench, and filling a conducting material layer into the second trench, thereby forming a first gate electrode.

Abstract: A fabricating method of a trench-gate metal oxide semiconductor device is provided. The fabricating method includes the steps of defining a first zone and a second zone in a substrate, forming at least one first trench in the second zone, forming a dielectric layer on the first zone and the second zone, filling the dielectric layer in the first trench, performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask, forming a first gate dielectric layer on a sidewall of the second trench, and filling a conducting material layer into the second trench, thereby forming a first gate electrode.

Abstract: A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 ?. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer.

Abstract: A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 ?. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer.