Patents by Inventor Kuan-Ting Chen

Kuan-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170553
    Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers, first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, a stack of second channel layers stacked over the first channel layers, third and fourth S/D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, and a dielectric isolation layer disposed under the first and second S/D epitaxial features. A total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers. The dielectric isolation layer is in physical contact with at least a bottommost one of the first channel layers.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 23, 2024
    Inventors: Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng
  • Publication number: 20240170337
    Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Zhi-Chang LIN, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Kuan-Ting PAN, Jung-Hung CHANG, Lo-Heng CHANG, Chien Ning YAO
  • Patent number: 11990471
    Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
  • Publication number: 20240147405
    Abstract: A controlling method for a wireless communication device is provided. The controlling method for the wireless communication device includes: attaching a first Universal Subscriber Identity Module (USIM) to a Long-Term Evolution (LTE) network; determining whether a second USIM is camped on the LTE network; detecting whether a paging collision is happened, if the second USIM is camped on the LTE network; generating a requested International Mobile Subscriber Identity (IMSI) offset for the second USIM, if the paging collision is happened, wherein the requested IMSI offset is 1 or min(T, nB)?1, T is a default paging period and nB is a number of paging occurrences within the default paging period; transmitting an attach request with the requested IMSI offset to the LTE network for the second USIM; receiving a negotiated IMSI offset from the LTE network; and attaching the second USIM to the LTE network with the negotiated IMSI offset.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Yu LIN, Ya-ling Hsu, Wan-Ting Huang, Yi-Han CHUNG, Yi-Cheng CHEN
  • Patent number: 11971609
    Abstract: A photographing optical system includes eight lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. The eight lens elements each have an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has positive refractive power. The fifth lens element has positive refractive power. The object-side surface of the seventh lens element is convex in a paraxial region thereof. The image-side surface of the eighth lens element is concave in a paraxial region thereof. At least one lens surface of at least one lens element of the photographing optical system has at least one critical point in an off-axis region thereof.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: April 30, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Chun-Yen Chen, Kuan-Ting Yeh, Tzu-Chieh Kuo
  • Patent number: 11972956
    Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
  • Patent number: 11966031
    Abstract: An image lens assembly includes, in order from an object side to an image side along an optical path, a first lens group, a second lens group, a third lens group and a fourth lens group. A total number of lens elements in the image lens assembly is seven. The first lens group includes a first lens element with positive refractive power and a second lens element with negative refractive power. Each of the second lens group and the third lens group includes at least one lens element. The fourth lens group includes a seventh lens element. When the image lens assembly is focusing or zooming, a relative position between the first lens group and an image surface is fixed, a relative position between the fourth lens group and the image surface is fixed, and the second lens group and the third lens group move along the optical axis.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: April 23, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting Yeh, Wei-Yu Chen
  • Publication number: 20240124715
    Abstract: A biomass treatment method includes steps as follows. A biomass and sodium percarbonate are provided, wherein the biomass includes hemicellulose, cellulose and/or lignin. The biomass and the sodium percarbonate are mixed.
    Type: Application
    Filed: March 7, 2023
    Publication date: April 18, 2024
    Applicant: National Cheng Kung University
    Inventors: Wei-Hsin Chen, Kuan-Ting Lee
  • Publication number: 20240118522
    Abstract: A photographing lens assembly includes, in order from an object side to an image side: a first, a second, a third, a fourth, a fifth and a sixth lens elements. The first lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, wherein the object-side surface has at least one convex critical point in an off-axis region thereof. The third lens element has an image-side surface being convex in a paraxial region thereof. The fourth lens element has positive refractive power. The fifth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, and an image-side surface being convex in a paraxial region thereof. The sixth lens element has an image-side surface being concave in a paraxial region thereof, wherein the image-side surface has at least one convex critical point in an off-axis region thereof.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 11, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Po-Lun HSU, Wei-Yu CHEN, Kuan-Ting YEH, Ssu-Hsin LIU
  • Publication number: 20240109203
    Abstract: End effector tool changers for a robotic system are disclosed. The end effector tool changer is physically compact, mechanically robust, has high radial strength, prevents undesirable rotations, uses minimal sensory input, is suitable for a wide variety of tools, and operates quickly. The end effector tool changer includes a robotic arm attachment portion, including a first magnetic part and a plurality of first engagement parts, and a tool attachment portion, including a second magnetic part and a plurality of second engagement parts, where the plurality of first engagement parts is configured to engage with the plurality of second engagement parts, each of the plurality of first engagement parts and each of the plurality of second engagement parts are selected from the group consisting of a pin and a pin groove, and the first magnetic part spatially and magnetically corresponds to the second magnetic part.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Kuan-Ting Yu, Shao-Yu Chen
  • Patent number: 11948989
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ting Chung, Yi-Bo Liao, Hou-Yu Chen, Kuan-Lun Cheng
  • Patent number: 11947634
    Abstract: An image object classification method and system are disclosed. The method is executed by a processor coupled to a memory. The method includes: providing an image file including at least one image object, performing a process of extracting multiple binary-classified characteristics on the image object to obtain a plurality of first results independent of each other in categories, combining the plurality of first results in a manner of dimensionality reduction based on concatenation, performing a process of characteristics abstraction on the combined first results to obtain a second result, and performing a process of characteristics integration on the plurality of first results and the second result in a manner of dot product of matrices to obtain a classification result.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 2, 2024
    Assignee: Footprintku Inc.
    Inventors: Yan-Jhih Wang, Kuan-Hsiang Tseng, Jun-Qiang Wei, Shih-Feng Huang, Tzung-Pei Hong, Yi-Ting Chen
  • Patent number: 11942546
    Abstract: A method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: March 26, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Kuan-Ting Chen, Shu-Tong Chang, Min-Hung Lee
  • Patent number: 11940597
    Abstract: An image capturing optical lens system includes four lens elements, which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element and a fourth lens element. The first lens element has an object-side surface being convex in a paraxial region thereof. The third lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The fourth lens element has negative refractive power.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: March 26, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting Yeh, Wei-Yu Chen
  • Publication number: 20240096883
    Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu
  • Publication number: 20240088144
    Abstract: A gate structure includes a metal layer, a barrier layer, and a work function layer. The barrier layer covers a bottom surface and sidewalls of the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. The work function layer surrounds the barrier layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu
  • Patent number: 11929287
    Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Kuan-Ting Pan, Jung-Hung Chang, Lo-Heng Chang, Chien Ning Yao
  • Patent number: 11916122
    Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Kuan-Ting Pan, Shih-Cheng Chen, Jung-Hung Chang, Lo-Heng Chang, Chien-Ning Yao, Kuo-Cheng Chiang
  • Publication number: 20230386371
    Abstract: A display method and a display system for an anti-dizziness reference image are provided. The display system includes a display, a range extraction unit, an information analyzing unit, an object analyzing unit and an image setting unit. The display is used to display the anti-dizziness reference image. The range extraction unit is used to obtain a gaze background range of a user. The image setting unit is used to set an image hue, an image lightness, an image brightness, an image content or an ambient lighting display content of the anti-dizziness reference image according to a background hue information, a background lightness information, a background brightness information, or a road information of the gaze background range; or set an image ratio between the anti-dizziness reference image and a display area of the display according to an object distance or an object area of the watched object.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 30, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ya-Rou HSU, Chien-Ju LEE, Hong-Ming DAI, Yu-Hsiang TSAI, Chia-Hsun TU, Kuan-Ting CHEN
  • Patent number: D1027976
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 21, 2024
    Assignee: VIVOTEK INC.
    Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung