Patents by Inventor Kuan-Wei Chuang
Kuan-Wei Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990522Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.Type: GrantFiled: December 9, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 11978782Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.Type: GrantFiled: June 9, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 9548220Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: GrantFiled: January 4, 2016Date of Patent: January 17, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Publication number: 20160118271Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: January 4, 2016Publication date: April 28, 2016Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Publication number: 20160079110Abstract: A semiconductor package is provided, which includes: a carrier; a frame having a plurality of openings, wherein the frame is bonded to the carrier and made of a material different from that of the carrier; a plurality of electronic elements disposed in the openings of the frame, respectively; an encapsulant formed in the openings of the frame for encapsulating the electronic elements; and a circuit layer formed on and electrically connected to the electronic elements. By accurately controlling the size of the openings of the frame, the present invention increases the accuracy of positioning of the electronic elements so as to improve the product yield in subsequent processes.Type: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Inventors: Kuan-Wei Chuang, Shih-Kuang Chiu, Chun-Tang Lin, Jung-Pang Huang
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Patent number: 9257381Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: GrantFiled: December 20, 2012Date of Patent: February 9, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Patent number: 8895367Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: GrantFiled: August 12, 2013Date of Patent: November 25, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
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Publication number: 20140127864Abstract: A method of fabricating a semiconductor package is provided, including providing an interposer having a plurality of conductive elements, disposing the interposer on a carrier having a plurality of recessed portions for the conductive elements to be received therein such that the interposer is coupled to the carrier, attaching the semiconductor element to the interposer, and removing the carrier. Coupling the interposer to the carrier prevents the conductive elements from displacement under pressure. Therefore, the conductive elements will not be in poor or no electrical contact with the interposer.Type: ApplicationFiled: December 28, 2012Publication date: May 8, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Che Lai
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Publication number: 20140077387Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: November 20, 2012Publication date: March 20, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi Che Lai
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Publication number: 20140070424Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: December 20, 2012Publication date: March 13, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Publication number: 20130330883Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: ApplicationFiled: August 12, 2013Publication date: December 12, 2013Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
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Patent number: 8519526Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: GrantFiled: May 20, 2011Date of Patent: August 27, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
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Publication number: 20120161301Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: ApplicationFiled: May 20, 2011Publication date: June 28, 2012Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
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Patent number: D1027976Type: GrantFiled: May 24, 2021Date of Patent: May 21, 2024Assignee: VIVOTEK INC.Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung