Patents by Inventor Kuan-Wen FONG

Kuan-Wen FONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210159142
    Abstract: A chip package structure includes a circuit structure, a redistribution structure, a heat conductive component, a chip, and a heat sink. The circuit structure includes a first circuit layer. The redistribution structure is disposed on the circuit structure and includes a second circuit layer, wherein the redistribution structure has an opening. The heat conductive component is disposed on the circuit structure and covered by the redistribution structure. The heat conductive component has a horizontal portion and a vertical portion. The horizontal portion extends toward the opening until it exceeds the opening. The vertical portion extends upward beyond the top surface of the redistribution structure from a part of the horizontal portion. The chip is disposed in the opening, and the bottom of the chip contacts the heat conductive component. The heat sink is disposed over the redistribution structure and the chip.
    Type: Application
    Filed: February 2, 2021
    Publication date: May 27, 2021
    Inventors: Tzu-Hsuan WANG, Chien-Chen LIN, Kuan-Wen FONG
  • Patent number: 10964634
    Abstract: A circuit carrier with embedded substrate includes a circuit structure and an embedded substrate. The circuit structure includes a first dielectric layer, a first patterned circuit layer, a trench, and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is embedded in the first surface. The first bumps are disposed on the first surface and electrically connected to the first patterned circuit layer. The trench exposes a portion of the first dielectric layer. The embedded substrate is disposed in the trench and includes a plurality of second bumps. A chip package structure includes the above circuit carrier with embedded substrate.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 30, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chien-Chen Lin, Tzu-Hsuan Wang, Kuan-Wen Fong
  • Patent number: 10943846
    Abstract: A chip package structure includes a circuit structure, a redistribution structure, a heat conductive component, a chip, and a heat sink. The circuit structure includes a first circuit layer. The redistribution structure is disposed on the circuit structure and includes a second circuit layer, wherein the redistribution structure has an opening. The heat conductive component is disposed on the circuit structure and covered by the redistribution structure. The heat conductive component has a horizontal portion and a vertical portion. The horizontal portion extends toward the opening until it exceeds the opening. The vertical portion extends upward beyond the top surface of the redistribution structure from a part of the horizontal portion. The chip is disposed in the opening, and the bottom of the chip contacts the heat conductive component. The heat sink is disposed over the redistribution structure and the chip.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 9, 2021
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tzu-Hsuan Wang, Chien-Chen Lin, Kuan-Wen Fong
  • Publication number: 20200126883
    Abstract: A chip package structure includes a circuit structure, a redistribution structure, a heat conductive component, a chip, and a heat sink. The circuit structure includes a first circuit layer. The redistribution structure is disposed on the circuit structure and includes a second circuit layer, wherein the redistribution structure has an opening. The heat conductive component is disposed on the circuit structure and covered by the redistribution structure. The heat conductive component has a horizontal portion and a vertical portion. The horizontal portion extends toward the opening until it exceeds the opening. The vertical portion extends upward beyond the top surface of the redistribution structure from a part of the horizontal portion. The chip is disposed in the opening, and the bottom of the chip contacts the heat conductive component. The heat sink is disposed over the redistribution structure and the chip.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 23, 2020
    Inventors: Tzu-Hsuan WANG, Chien-Chen LIN, Kuan-Wen FONG
  • Publication number: 20200075469
    Abstract: A circuit carrier with embedded substrate includes a circuit structure and an embedded substrate. The circuit structure includes a first dielectric layer, a first patterned circuit layer, a trench, and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is embedded in the first surface. The first bumps are disposed on the first surface and electrically connected to the first patterned circuit layer. The trench exposes a portion of the first dielectric layer. The embedded substrate is disposed in the trench and includes a plurality of second bumps. A chip package structure includes the above circuit carrier with embedded substrate.
    Type: Application
    Filed: October 17, 2018
    Publication date: March 5, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Chien-Chen Lin, Tzu-Hsuan Wang, Kuan-Wen Fong
  • Publication number: 20200029433
    Abstract: A substrate structure includes a first circuit structure, a second dielectric layer, and a second circuit structure. The first circuit structure includes a first layer and a second layer. The first layer includes a first dielectric layer and a first circuit layer embedded in the first dielectric layer. The second layer is disposed below the first layer and includes a second circuit layer electrically connected to the first circuit layer. The second dielectric layer is disposed on the first circuit structure and has a first opening exposing a portion of the first circuit layer. The melting point of the second dielectric layer is lower than that of the first dielectric layer. The second circuit structure is disposed on the second dielectric layer and has a second opening connected to the first opening. The second circuit structure includes a third circuit layer electrically connected to the first circuit layer.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 23, 2020
    Inventors: Chien-Chen LIN, Kuan-Wen FONG