Abstract: A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a plurality shallow trench isolation structures. A thin insulating layer and a conducting layer are formed in the trenches. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench. The MOSFET device has at least the following structures. There is a substrate with an active region and a non-active region, wherein the active region has a plurality of trenches and the non-active region has a plurality of shallow trench isolation structures.

Abstract: A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a plurality shallow trench isolation structures. A thin insulating layer and a conducting layer are formed in the trenches. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench. The MOSFET device has at least the following structures. There is a substrate with an active region and a non-active region, wherein the active region has a plurality of trenches and the non-active region has a plurality of shallow trench isolation structures.

Abstract: A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a plurality shallow trench isolation structures. A thin insulating layer and a conducting layer are formed in the trenches. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench. The MOSFET device has at least the following structures. There is a substrate with an active region and a non-active region, wherein the active region has a plurality of trenches and the non-active region has a plurality of shallow trench isolation structures.

Abstract: A method of manufacturing buried gates by performing two trench-forming operations. The method includes forming a first trench in a substrate, and then forming a dielectric layer over the substrate and the interior surface of the first trench. Next, conductive material is deposited into the first trench. Thereafter, second trenches are formed crossing the first trench alternately, wherein the second trenches has a depth greater than the depth of the first trench. Subsequently, insulation material is deposited into the second trenches simultaneously forming buried gates and isolation structures. Floating and control gates are then formed over the buried gates. A similar method can be used to form buried conductive layer by omitting the formation of the dielectric layer.

Abstract: A method of testing EM lifetime has following steps. First, a pre-characterizing step is performed to obtain parameters such as TC(the critical temperature,), Wc (the critical line width), QGB(the activation energy of grain boundary diffusion) and QL(the activation energy of lattice diffusion) of a metal prior to the use of the test methodology for a new technology. Next, whether a real line width (W) of the metal is narrower or wider than WC is determined. For the narrower line widths, the diffusion mechanism is dominated by the Lattice diffusion only and corresponds to single activation energy (QL). A WLR isothermal test with a relatively high temperature, such as 400° C., can be implemented to reduce the test time to as short as a few seconds. The EM lifetime (t50) under normal operating condition can be directly obtained by conversion from Ttest to TC by using QL.

Abstract: A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a plurality shallow trench isolation structures. A thin insulating layer and a conducting layer are formed in the trenches. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench. The MOSFET device has at least the following structures. There is a substrate with an active region and a non-active region, wherein the active region has a plurality of trenches and the non-active region has a plurality of shallow trench isolation structures.

Abstract: A method of manufacturing buried gates by performing two trench-forming operations. The method includes forming a first trench in a substrate, and then forming a dielectric layer over the substrate and the interior surface of the first trench. Next, conductive material is deposited into the first trench. Thereafter, second trenches are formed crossing the first trench alternately, wherein the second trenches has a depth greater than the depth of the first trench. Subsequently, insulation material is deposited into the second trenches simultaneously forming buried gates and isolation structures. Floating and control gates are then formed over the buried gates. A similar method can be used to form buried conductive layer by omitting the formation of the dielectric layer.

Abstract: A statistical method of monitoring the yield of a gate oxide layer. A voltage is applied to first test keys and second test keys to build curves showing relationship between failure distribution and charge density, wherein each of the first test keys has a first oxide area and each of the second test keys has a second oxide area. A yield of the first test keys and a yield of the second test keys up to a charge density can be obtained. The yields of the first test keys and the second test keys have a relationship as an equation of area. To obtain a yield of small test keys, a yield and area of large test keys are imported into an equation. According to operating the equation, the yield of a small gate oxide is obtained.

Abstract: A fabrication method for an oxide layer with reduced interface-trapped charges, which is applicable to the fabrication of a gate oxide layer of a flash memory device, is described. The method includes conducting a first inert ambient annealing process, followed by growing an oxide layer on the silicon substrate. A second inert ambient annealing process is then conducted on the oxide layer. Carbon ions are then incorporated into the interface between the oxide layer and the silicon substrate, followed by a third ambient annealing process.

Abstract: A method for testing the reliability of a dielectric thin film. An exponential current ramp test is performed with a delay time to test the dielectric thin film. An exponential current ramp charge-to-breakdown distribution, which is represented by cumulative distribution failure percentage, is obtained. An exponential current ramp charge-to-breakdown at a cumulative distribution failure percentage is calculated. An exponential current ramp constant and a constant current stress constant at the cumulative distribution failure percentage are calculated. A constant current stress charge-to-breakdown at the cumulative distribution failure percentage is calculated by using a specified current density and the constant current stress constant at the cumulative distribution failure percentage. The constant current stress charge-to-breakdown at the cumulative distribution failure percentage is compared to a specified constant current stress charge-to-breakdown to determine the reliability of the dielectric thin film.

Abstract: A retrograde ESD (electrostatic discharge) protection apparatus is disclosed. In a MOSFET (metal-oxide-semiconductor field effect transistor) having a source region, a drain region, a gate region, and a LDD (Lightly-Doped Drain) region, the ESD protection regions are implanted using heavy doped method under LDD region such that the implantation profile is optimized. The optimized profile is that the concentration of ESD protection region is heaviest at the source/drain junction region.

Abstract: A method is described for taking a lifetime measurement of an ultra-thin dielectric layer. In order to discover the life time of the ultra-thin dielectric layer, the measurement comprises using about one half of a stress voltage to measure a time-dependent leakage current of the ultra-thin dielectric layer.

Abstract: A method for preventing horizontal and vertical crosstalk between conductive layers forms a dummy conductive layer between conductive layers and between conductive lines within a dielectric layer. The dummy conductive layer does not connect with conductive layers or conductive lines. Because the dummy conductive layer has a shielding effect for conductive layers, the method can reduce the horizontal and vertical crosstalk between conductive layers.

Abstract: A bi-directional transistor structure is provided, which can help solve the problem of degraded performance due to hot carrier injection (HCI) effect that is otherwise prominent in conventional bi-directional transistors.

Abstract: A device manufacturing method prevents damage from plasma charging and vertical cross talk. The method comprises the steps of forming an insulating layer over a substrate that has a MOS device and source/drain regions already formed thereon. The insulating layer is formed by a non-plasma operation so that plasma damage is avoided. Thereafter, a conductive layer is formed over the substrate. The conductive layer is used to channel away excess charges produced during subsequent plasma operations, thereby balancing electric potential and preventing damage to the device from current flow. Subsequently, an inter-layer dielectric layer is formed over the conductive layer, and then the inter-layer dielectric layer, the conductive layer and the insulating layer are patterned to form an opening that exposes the source/drain region.

Abstract: A layout design for an electrostatic discharge protection device formed above a first type of semiconductor substrate. This electrostatic discharge protection device comprises a gate region having a tortuous but continuous structure located above the first type semiconductor substrate, a common source region in the first type semiconductor substrate located on one side of the gate region, a multiple of separate drain regions in the first type semiconductor substrate located on the other side of the gate region, a multiple of contact openings distributed over the common source region and the drain regions, and, a conductive runner having a width narrower than the drain region electrically connected to each drain region.

Abstract: A method for forming high voltage devices is provided. A P-type semiconductor substrate is provided. An oxide layer is formed on the P-type semiconductor substrate. A first P-well and a second P-well are formed in the P-type semiconductor substrate. A first N-well is formed in the second p-well and a second N-well is formed in the first P-well. A field oxide layer on the second N-well and a gate oxide layer are formed on the P-type substrate. A polysilicon layer is formed and defined as a gate on the gate oxide layer across a portion of the field oxide layer and aportion of the first N-well. A source region is formed in the first N-well and a drain region is formed in the second N-well. A P.sup.+ -type doped region is formed between the substrate and the source region across a part of the first N-well within the second P-well.

Abstract: An electrically erasable programmable read only flash memory having a buried floating gate structure buries the floating gate within the substrate. The source and drain regions are located beside the floating gate, and the control gate is located on the surface of the substrate and above the floating gate. In the program mode of read only flash memory based on the structure of this invention, the tunneling effect occurs between the floating gate and control gate to reduce leakage current and to raise the programming rate, which has the advantage of increasing the integration of memory cells.

Abstract: A protection circuit using point discharge suitable for use in an integrated circuit, protects circuit from damage by electrostatic discharge. The integrated circuit at least comprises an input/output port, a high voltage line, and a low voltage line. The protection circuit has point discharge structures at two ends of the input/output ports, respectively corresponding to the point discharge structures of the high and low voltage lines, and is suitable for use in all semiconductor fabricating processes.

Abstract: A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a plurality shallow trench isolation structures. A thin insulating layer and a conducting layer are formed in the trenches. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench. The MOSFET device has at least the following structures. There is a substrate with an active region and a non-active region, wherein the active region has a plurality of trenches and the non-active region has a plurality of shallow trench isolation structures.