Patents by Inventor KUAN-YU HUANG
KUAN-YU HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11075133Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: GrantFiled: November 1, 2018Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
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Publication number: 20210210400Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
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Publication number: 20210193538Abstract: A semiconductor structure and a method for fabricating the same are disclosed. A semiconductor structure includes a first substrate, a package, a second substrate, and a lid. The package is attached to a first side of the first substrate. The second substrate is attached to a second side of the first substrate. The lid is connected to the first substrate and the second substrate. The lid includes a ring part over the first side of the first substrate. The ring part and the first substrate define a space and the package is accommodated in the space. The lid further includes a plurality of overhang parts which extend from corner sidewalls of the ring part toward the second substrate to cover corner sidewalls of the first substrate.Type: ApplicationFiled: July 2, 2020Publication date: June 24, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Chien-Yuan Huang
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Patent number: 11024616Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.Type: GrantFiled: May 16, 2019Date of Patent: June 1, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Chen, Li-Chung Kuo, Long-Hua Lee, Szu-Wei Lu, Ying-Ching Shih, Kuan-Yu Huang
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Publication number: 20210132310Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.Type: ApplicationFiled: December 14, 2020Publication date: May 6, 2021Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20210125907Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.Type: ApplicationFiled: February 23, 2020Publication date: April 29, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
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Patent number: 10985125Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.Type: GrantFiled: September 23, 2020Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shu-Chia Hsu, Leu-Jen Chen, Yi-Wei Liu, Shang-Yun Hou, Jui-Hsieh Lai, Tsung-Yu Chen, Chien-Yuan Huang, Yu-Wei Chen
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Publication number: 20210066230Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu HUANG, Sung-Hui HUANG, Shang-Yun HOU
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Publication number: 20210005567Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.Type: ApplicationFiled: September 23, 2020Publication date: January 7, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu HUANG, Sung-Hui HUANG, Shu-Chia HSU, Leu-Jen CHEN, Yi-Wei LIU, Shang-Yun HOU, Jui-Hsieh LAI, Tsung-Yu CHEN, Chien-Yuan HUANG, Yu-Wei CHEN
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Patent number: 10886147Abstract: A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.Type: GrantFiled: September 16, 2019Date of Patent: January 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
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Publication number: 20200402926Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Inventors: Sung-Hui Huang, Da-Cyuan Yu, Kuan-Yu Huang, Pai Yuan Li, Hsiang-Fan Lee
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Patent number: 10872871Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate.Type: GrantFiled: May 7, 2019Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Hui Huang, Kuan-Yu Huang, Shang-Yun Hou, Yushun Lin, Heh-Chang Huang, Shu-Chia Hsu, Pai-Yuan Li, Kung-Chen Yeh
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Patent number: 10867951Abstract: A semiconductor device includes an electronic component, a package, a substrate and a plurality of first conductors and second conductors. The package is over the electronic component. T substrate is between the electronic component and the package. The substrate includes a first portion covered by the package, and a second portion protruding out of an edge of the package and uncovered by the package. The first conductors and second conductors are between and electrically connected to the electronic component and the substrate. A width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors, the first conductors are disposed between the second portion of the substrate and the electronic component, and the second conductors are disposed between the first portion of the substrate and the electronic component.Type: GrantFiled: April 16, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuan-Yu Huang, Tzu-Kai Lan, Shou-Chih Yin, Shu-Chia Hsu, Pai-Yuan Li, Sung-Hui Huang, Hsiang-Fan Lee, Ying-Shin Han
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Patent number: 10866373Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.Type: GrantFiled: June 25, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Patent number: 10847485Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.Type: GrantFiled: May 28, 2019Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
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Publication number: 20200365571Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.Type: ApplicationFiled: May 16, 2019Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Wei Chen, Li-Chung Kuo, Long-Hua Lee, Szu-Wei Lu, Ying-Ching Shih, Kuan-Yu Huang
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Patent number: 10790254Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.Type: GrantFiled: February 15, 2019Date of Patent: September 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shu-Chia Hsu, Leu-Jen Chen, Yi-Wei Liu, Shang-Yun Hou, Jui-Hsieh Lai, Tsung-Yu Chen, Chien-Yuan Huang, Yu-Wei Chen
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Patent number: 10770405Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.Type: GrantFiled: May 31, 2017Date of Patent: September 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Hui Huang, Da-Cyuan Yu, Kuan-Yu Huang, Pai Yuan Li, Hsiang-Fan Lee
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Publication number: 20200251427Abstract: A semiconductor device includes a substrate, an electronic component, a ring structure and an adhesive layer. The substrate has a first surface. The electronic component is over the first surface of the substrate. The ring structure is over the first surface of the substrate, wherein the ring structure includes a first part having a first height, and a second part recessed from the bottom surface and having a second height lower than the first height. The adhesive layer is interposed between the first part of the ring structure and the substrate, and between the second part of the ring structure and the substrate.Type: ApplicationFiled: April 21, 2020Publication date: August 6, 2020Inventors: KUAN-YU HUANG, SUNG-HUI HUANG, PAI-YUAN LI, SHU-CHIA HSU, HSIANG-FAN LEE, SZU-PO HUANG
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Patent number: 10707177Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.Type: GrantFiled: July 30, 2018Date of Patent: July 7, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Hui Huang, Da-Cyuan Yu, Kuan-Yu Huang, Pai Yuan Li, Hsiang-Fan Lee