Patents by Inventor Kuan-Yu Wang
Kuan-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996293Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin protruding from the substrate, an isolation feature disposed on the substrate and on sidewalls of the first and second semiconductor fins, a gate structure disposed on the isolation feature. The semiconductor device also includes a dielectric fin disposed on the isolation feature and sandwiched between the first and second semiconductor fins. A middle portion of the dielectric fin separates the gate structure into a first gate structure segment engaging the first semiconductor fin and a second gate structure segment engaging the second semiconductor fin.Type: GrantFiled: August 2, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
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Publication number: 20240137049Abstract: A millimeter wave signal transmission integration device includes an antenna array module, a flexible substrate, a coaxial cable and a signal processing module. The antenna array module is used to transmit and receive millimeter wave signals, and convert millimeter wave signals to intermediate frequency (IF) signals or convert IF signals to millimeter wave signals. The flexible substrate is connected to the antenna array module, and is used to transmit/receive IF signals. The coaxial cable is connected to the flexible substrate and is used to transmit and receive IF signals. The signal processing module is connected to the coaxial cable and is used to transmit and receive IF signals. With the above configuration, the present invention achieves the effects of reduced occupied space of the millimeter wave signal transmission module and reduced attenuation of IF signals.Type: ApplicationFiled: February 28, 2023Publication date: April 25, 2024Inventors: KUAN-YU CHEN, MIN-YU WANG
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Patent number: 11948879Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.Type: GrantFiled: July 27, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11929418Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.Type: GrantFiled: November 11, 2021Date of Patent: March 12, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
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Publication number: 20240072115Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.Type: ApplicationFiled: February 13, 2023Publication date: February 29, 2024Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
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Patent number: 11916128Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.Type: GrantFiled: February 27, 2023Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20220384267Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi LEE, Kuan-Yu WANG, Cheng-Lung HUNG, Chi-On CHUI
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Patent number: 11450569Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.Type: GrantFiled: September 18, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi Lee, Kuan-Yu Wang, Cheng-Lung Hung, Chi-On Chui
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Publication number: 20220093468Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi LEE, Kuan-Yu WANG, Cheng-Lung HUNG, Chi-On CHUI
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Patent number: 10927000Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.Type: GrantFiled: October 17, 2016Date of Patent: February 23, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
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Patent number: 10804664Abstract: The invention is related to a crimp tool having an adjustable cam for accomplishing precision machining of a connector with a cable. The adjustable cam is provided at one of the handles of the crimp tool and is configured to prevent a moving handle of the crimp tool from moving beyond the adjustable cam so as to allow a user to adjust the pivot range of the moving handle, which controls the extent of the movement of a machining block in a machining portion of the crimp tool.Type: GrantFiled: December 5, 2017Date of Patent: October 13, 2020Inventors: Robert W. Sullivan, Kuan Yu Wang, Wen-Lung Hung
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Patent number: 10475640Abstract: Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.Type: GrantFiled: September 21, 2018Date of Patent: November 12, 2019Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yan-Da Chen, Weng Yi Chen, Chang-Sheng Hsu, Kuan-Yu Wang, Yuan Sheng Lin
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Patent number: 10457546Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.Type: GrantFiled: March 14, 2018Date of Patent: October 29, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu
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Patent number: 10427935Abstract: A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.Type: GrantFiled: September 21, 2018Date of Patent: October 1, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
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Publication number: 20190027358Abstract: Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.Type: ApplicationFiled: September 21, 2018Publication date: January 24, 2019Inventors: YAN-DA CHEN, WENG YI CHEN, CHANG-SHENG HSU, KUAN-YU WANG, YUAN SHENG LIN
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Publication number: 20190016591Abstract: A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.Type: ApplicationFiled: September 21, 2018Publication date: January 17, 2019Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
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Patent number: 10115582Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.Type: GrantFiled: June 5, 2015Date of Patent: October 30, 2018Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yan-Da Chen, Weng Yi Chen, Chang-Sheng Hsu, Kuan-Yu Wang, Yuan Sheng Lin
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Patent number: 10112825Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.Type: GrantFiled: March 3, 2017Date of Patent: October 30, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
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Publication number: 20180208460Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.Type: ApplicationFiled: March 3, 2017Publication date: July 26, 2018Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
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Publication number: 20180201498Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.Type: ApplicationFiled: March 14, 2018Publication date: July 19, 2018Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu