Patents by Inventor Kuang-Chu Chen
Kuang-Chu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11980096Abstract: A semiconductor device includes a substrate. The semiconductor device also includes a semiconductor layer disposed in the substrate. The semiconductor device further includes a first dielectric layer disposed on the semiconductor layer. The semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a pair of thermopile segments disposed on the second dielectric layer. The first dielectric layer and the second dielectric layer form a chamber.Type: GrantFiled: August 21, 2020Date of Patent: May 7, 2024Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: In-Shiang Chiu, Kuang-Chu Chen, Peng-Chan Hsiao, Han-Ying Liu
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Patent number: 11856855Abstract: Provided are a thermal sensor and a manufacturing method thereof. The thermal sensor includes a transistor and a thermal sensing device. The thermal sensing device is disposed in a recess in a substrate and electrically connected to the transistor. The thermal sensing device includes a first dielectric layer, a metal silicide reflective layer, a second dielectric layer, and a thermal absorbing layer. The first dielectric layer is disposed on sidewalls and a bottom of the recess. The metal silicide reflective layer is disposed on the first dielectric layer located on the bottom of the recess. The second dielectric layer is disposed at a top of the recess. The thermal absorbing layer is disposed on the second dielectric layer.Type: GrantFiled: August 20, 2020Date of Patent: December 26, 2023Assignee: Nuvoton Technology CorporationInventors: In-Shiang Chiu, Kuang-Chu Chen, Peng-Chan Hsiao, Han-Ying Liu
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Patent number: 11561145Abstract: A sensor membrane structure is provided. The sensor membrane structure includes a substrate, a first insulating layer, and a device layer. The substrate has a first surface and a second surface that is opposite to the first surface. A cavity is formed on the first surface, an opening is formed on the second surface, and the cavity communicates with the opening. The cavity and the opening penetrate the substrate in a direction that is perpendicular to the first surface. The first insulating layer is disposed on the first surface of the substrate. The device layer is disposed on the first insulating layer. The first insulating layer is disposed for protecting the sensor membrane structure from overetched and remain stable during the etching process, increasing the yield of the sensor membrane structure.Type: GrantFiled: October 1, 2020Date of Patent: January 24, 2023Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Chung-Lung Hsu, Kuang-Chu Chen, Peng-Chan Hsiao, Han-Ying Liu
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Patent number: 11502195Abstract: A semiconductor structure and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes a substrate and a III-V group compound layer disposed on the substrate. The III-V group compound layer has n trenches vertically communicating with each other, and n?2. Widths of the n trenches gradually decrease from the width of the uppermost first trench to the width of the lowermost nth trench, and the nth trench exposes a portion of the substrate.Type: GrantFiled: September 3, 2020Date of Patent: November 15, 2022Assignee: Nuvoton Technology CorporationInventors: Ching-San Wang, Kuang-Chu Chen, Peng-Chan Hsiao, Han-Ying Liu
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Publication number: 20210199524Abstract: A sensor membrane structure is provided. The sensor membrane structure includes a substrate, a first insulating layer, and a device layer. The substrate has a first surface and a second surface that is opposite to the first surface. A cavity is formed on the first surface, an opening is formed on the second surface, and the cavity communicates with the opening. The cavity and the opening penetrate the substrate in a direction that is perpendicular to the first surface. The first insulating layer is disposed on the first surface of the substrate. The device layer is disposed on the first insulating layer.Type: ApplicationFiled: October 1, 2020Publication date: July 1, 2021Inventors: Chung-Lung HSU, Kuang-Chu CHEN, Peng-Chan HSIAO, Han-Ying LIU
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Publication number: 20210202739Abstract: A semiconductor structure and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes a substrate and a III-V group compound layer disposed on the substrate. The III-V group compound layer has n trenches vertically communicating with each other, and n?2. Widths of the n trenches gradually decrease from the width of the uppermost first trench to the width of the lowermost nth trench, and the nth trench exposes a portion of the substrate.Type: ApplicationFiled: September 3, 2020Publication date: July 1, 2021Applicant: Nuvoton Technology CorporationInventors: Ching-San Wang, Kuang-Chu Chen, Peng-Chan Hsiao, Han-Ying Liu
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Publication number: 20210190601Abstract: Provided are a thermal sensor and a manufacturing method thereof. The thermal sensor includes a transistor and a thermal sensing device. The thermal sensing device is disposed in a recess in a substrate and electrically connected to the transistor. The thermal sensing device includes a first dielectric layer, a metal silicide reflective layer, a second dielectric layer, and a thermal absorbing layer. The first dielectric layer is disposed on sidewalls and a bottom of the recess. The metal silicide reflective layer is disposed on the first dielectric layer located on the bottom of the recess. The second dielectric layer is disposed at a top of the recess. The thermal absorbing layer is disposed on the second dielectric layer.Type: ApplicationFiled: August 20, 2020Publication date: June 24, 2021Applicant: Nuvoton Technology CorporationInventors: In-Shiang Chiu, Kuang-Chu Chen, Peng-Chan Hsiao, Han-Ying Liu
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Publication number: 20210135082Abstract: A semiconductor device is provided. The semiconductor device includes a substrate. The semiconductor device also includes a semiconductor layer disposed in the substrate. The semiconductor device further includes a first dielectric layer disposed on the semiconductor layer. The semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a pair of thermopiles disposed on the second dielectric layer. The first dielectric layer and the second dielectric layer form a chamber.Type: ApplicationFiled: August 21, 2020Publication date: May 6, 2021Inventors: In-Shiang CHIU, Kuang-Chu CHEN, Peng-Chan HSIAO, Han-YING LIU
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Publication number: 20210134879Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a chamber. The semiconductor device also includes a first dielectric layer disposed on the substrate. The semiconductor device further includes a pair of thermocouples disposed on the first dielectric layer. The semiconductor device includes a second dielectric layer disposed on the first dielectric layer and between the thermocouples. The semiconductor device also includes an absorber connected to the thermocouples.Type: ApplicationFiled: June 18, 2020Publication date: May 6, 2021Inventors: In-Shiang CHIU, Kuang-Chu CHEN, Peng-Chan HSIAO, Han-Ying LIU
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Patent number: 8455342Abstract: A mask ROM fabrication method which comprises steps: sequentially forming a gate dielectric layer and a first photoresist layer on a substrate; letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm; doping the substrate to form a plurality of embedded bit lines having a width of 243-365 nm; removing the first photoresist layer; sequentially forming a polysilicon layer and a second photoresist layer on the gate dielectric layer; and letting the light pass through a second phase shift mask to photolithographically form a plurality of polysilicon word lines on the polysilicon layer. Thereby is reduced the line width of mask ROM to 243-365 nm and decreased the area of mask ROM.Type: GrantFiled: October 17, 2011Date of Patent: June 4, 2013Assignees: Nyquest Technology Corporation Limited, Nuvoton Technology CorporationInventors: Kuang-Chu Chen, Cheng Tao Chen, Chung-Lung Hsu, Chun-Yao Chiu, Chin-Yung Chang
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Publication number: 20130095628Abstract: A mask ROM fabrication method which comprises steps: sequentially forming a gate dielectric layer and a first photoresist layer on a substrate; letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm; doping the substrate to form a plurality of embedded bit lines having a width of 243-365 nm; removing the first photoresist layer; sequentially forming a polysilicon layer and a second photoresist layer on the gate dielectric layer; and letting the light pass through a second phase shift mask to photolithographically form a plurality of polysilicon word lines on the polysilicon layer. Thereby is reduced the line width of mask ROM to 243-365 nm and decreased the area of mask ROM.Type: ApplicationFiled: October 17, 2011Publication date: April 18, 2013Inventors: Kuang-Chu Chen, Cheng Tao Chen, Chung-Lung Hsu, Chun-Yao Chiu, Chin-Yung Chang