Patents by Inventor Kuang Hann Lin
Kuang Hann Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8796840Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: GrantFiled: March 16, 2012Date of Patent: August 5, 2014Assignee: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Patent number: 8252633Abstract: The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package.Type: GrantFiled: February 22, 2011Date of Patent: August 28, 2012Assignee: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Publication number: 20120168932Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: ApplicationFiled: March 16, 2012Publication date: July 5, 2012Applicant: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Patent number: 8138597Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: GrantFiled: November 4, 2010Date of Patent: March 20, 2012Assignee: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Publication number: 20110171784Abstract: The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package.Type: ApplicationFiled: February 22, 2011Publication date: July 14, 2011Applicant: VISHAY GENERAL SEMICONDUCTOR LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Patent number: 7915728Abstract: The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package.Type: GrantFiled: July 12, 2007Date of Patent: March 29, 2011Assignee: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Publication number: 20110049700Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: ApplicationFiled: November 4, 2010Publication date: March 3, 2011Applicant: VISHAY GENERAL SEMICONDUCTOR LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Patent number: 7838985Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: GrantFiled: July 12, 2007Date of Patent: November 23, 2010Assignee: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Publication number: 20090014863Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: ApplicationFiled: July 12, 2007Publication date: January 15, 2009Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Publication number: 20090014862Abstract: The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package.Type: ApplicationFiled: July 12, 2007Publication date: January 15, 2009Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Patent number: 6927094Abstract: The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced. The method comprises the steps of: providing a bottom frame matrix including a plurality of bottom frame units, each of which unit comprises a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit comprises a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively; and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.Type: GrantFiled: May 30, 2003Date of Patent: August 9, 2005Assignee: General Semiconductor of Taiwan, Ltd.Inventors: Max Chen, Ching Lu Hsu, Kuang Hann Lin, Yan-Man Tsui
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Patent number: 6576985Abstract: The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced, by providing a bottom frame matrix including a plurality of bottom frame units, each of which unit includes a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit includes a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively; and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.Type: GrantFiled: January 18, 2001Date of Patent: June 10, 2003Assignee: General Semiconductor Taiwan, Ltd.Inventors: Max Chen, Ching Lu Hsu, Kuang Hann Lin, Yan-Man Tsui
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Patent number: 6068809Abstract: In a method of injection molding elements, a first step is to charge a molding compound into an injection nozzle via a side hole defined in the nozzle under the control of a mini-plunger which is selectively reciprocally movable within a bore of the injection nozzle. In a second step, the mini-plunger is reciprocally moved in the bore of the nozzle for injecting substantially the entire molding compound in the bore of the injection nozzle into at least one cavity of a mold via a separate gate passage defined in the mold. Each gate passage is a narrow capillary aperture that connects the bore of the injection nozzle with a different one of the at least one cavity of the mold. In a third step, the nozzle and the mold are separated after the molding compound in the gate passage is cured but before the molding compound in the at least one cavity of the mold is cured. In a fourth step the molded element is removed from the at least one cavity of the mold once the molding compound therein is cured.Type: GrantFiled: July 25, 1997Date of Patent: May 30, 2000Assignee: General Semiconductor, Inc.Inventors: Eugene Chen, Hohn Jong Hsiung, Kuang Hann Lin, Wing Lun Wong, Boon Meng Chan
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Patent number: 5698242Abstract: An injection molding apparatus includes a nozzle which is directly connected to a mold for injecting a molding material into the mold. The mold defines at least one cavity in the shape of a element to be molded and at least one gate passage, each gate passage interconnecting a separate cavity with the nozzle. The shape of the gate passage permits a rapid curing of any residual molding material, and permits separation of the mold and the nozzle before the molding material in each cavity is cured. The nozzle is then used for a subsequent procedure or molding process while the molding material in the cavity cures. The nozzle defines a first bore and a second bore arranged longitudinally in sequence, and a side hole for introducing the molding material into the first bore. The nozzle includes a first plunger which is selectively reciprocally movable in the first bore, and a second plunger which is selectively reciprocally movable in the second bore and in a central bore defined in the first plunger.Type: GrantFiled: December 20, 1995Date of Patent: December 16, 1997Assignees: General Instrument Corporation of Delaware, Kras Asia LtdInventors: Eugene Chen, Hohn Jong Hsiung, Kuang Hann Lin, Wing Lun Wong, Boon Meng Chan