Patents by Inventor Kuang-Ho Liao

Kuang-Ho Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6844616
    Abstract: A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: January 18, 2005
    Assignee: Vanguard International Semiconductor Corp.
    Inventors: Kuang-Ho Liao, Feng Lin, Yun-sheng Chen
  • Patent number: 6458617
    Abstract: A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: October 1, 2002
    Assignee: Vanguard International Semiconductor Corp.
    Inventors: Kuang-Ho Liao, Feng Lin, Yun-sheng Chen
  • Publication number: 20020089048
    Abstract: A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.
    Type: Application
    Filed: March 15, 2002
    Publication date: July 11, 2002
    Inventors: Kuang-Ho Liao, Feng Lin, Yun-Sheng Chen
  • Publication number: 20020074638
    Abstract: A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.
    Type: Application
    Filed: February 20, 2001
    Publication date: June 20, 2002
    Inventors: Kuang-Ho Liao, Feng Lin, Yun-sheng Chen
  • Patent number: 6245598
    Abstract: A method for forming chip scale packages and devices formed by utilizing a wire bonding technique and an interposer board which has recessed peripheral regions are disclosed. In the method, an IC die is bonded on its active surface to an interposer which is constructed with a recessed peripheral regions equipped with interconnections such that shorter bond wires may be run between the IC die and the interposer. The interposer is further equipped, in a top planar surface, with a plurality of interconnections for the subsequently forming of solder balls for connecting to an outside circuit such as a printed circuit board. The present invention novel method further provides the benefit that the shorter wire bonds formed alleviate the wire sweep problem normally occurs in the plastic encapsulation process for such a package.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: June 12, 2001
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Chieh Chen, Chun-Liang Chen, Kuang-Ho Liao
  • Patent number: 6220102
    Abstract: A new method and apparatus is provided for obtaining a quantitative reading of the strength of the chip bonding connections and for testing the quality of the bonding that is established between a chip and the chip pad or tapes on which the chip is mounted. The invention makes use of the fact that the lead frame, that is the frame that contains the leads to which the chip is connected, uses a material for the metal interconnects that can be controlled by a magnetic field. A metal alloy is commonly used to fabricate the interconnect leads on the lead frame. The alloy is typically selected based on considerations of thermal stress (between the chip and the chip pad or tapes or equivalent interface on which the chip is mounted) and on considerations of delamination between the lead frame and the encapsulating compound. Ni—Fe is an alloy that is frequently used as the material for the metal interconnects on the lead frame.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: April 24, 2001
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Kuang-Ho Liao
  • Patent number: 6122822
    Abstract: A method for forming a plastic package of an electronic device that is substantially without void formation is disclosed. In the method, a lead finger which is to be encapsulated in a plastic package is first deformed into various configurations such that the mold flow pattern can be modified accordingly. For instance, the tip portion of the lead finger can be formed into a U-shaped or a V-shaped bend, can be tilted to a 45.degree. slope or can be formed with U-shaped or V-shaped notch in the lead finger such that plastic flow velocity may be increased where the flow channel has been enlarged. Numerous embodiments of the present invention novel method are available for achieving similarly desirable results.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: September 26, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Kuang-Ho Liao
  • Patent number: 6075281
    Abstract: A lead frame equipped with modified lead fingers which have inclined tip portions for achieving an improved wire bond is provided. The inclined tip portions on the lead fingers can be formed in a stamping process with an angle on a top surface of the inclined tip portion measured at smaller than 30.degree. from a horizontal plane of the lead finger. It is preferred that the inclined angle should be between about 5.degree. and about 30.degree., and more preferred that the angle should be between about 5.degree. and about 20.degree.. A wedge bond formed on the inclined tip portion of a lead finger has improved thickness and thermal stress endurance. The thermal stress endurance may be improved by at least 20% and preferably by at least 50% when tested in a thermal cycling test between 150.degree. C. and -65.degree. C.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: June 13, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Kuang-Ho Liao, Tsung-Chieh Chen, Chuen-Jye Lin