Patents by Inventor Kuang Y. Chiu

Kuang Y. Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5401998
    Abstract: A P-type substrate is immersed in a solution of potassium hydroxide (KOH) which etches exposed portions of the substrate to form trenches with sidewalls at an angle of 54.7 degrees with respect to the top surface of the substrate. A vertical boron implant is then conducted which implants boron ions into the angled sidewalls of the trenches. A layer of oxide is then deposited over the substrate surface to fill the trenches approximately flush with the surface of the substrate. NMOS transistors may then be formed in the islands surrounded by the trenches so as to be isolated from other NMOS devices. The boron doping of the sidewalls prevents the inversion of the sidewalls due to any charged contaminants in the deposited oxide. This avoids parasitic leakage currents between the N-type source and drain regions of the NMOS transistors which abut the sidewalls of the trenches.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: March 28, 1995
    Inventors: Kuang Y. Chiu, Dan W. Peters
  • Patent number: 4843023
    Abstract: A new lightly doped drain (LDD) process which does not required extra masking steps as compared to the conventional CMOS process is presented. By employing a new two layer side wall spacer technology, the LDD ion implantation for n-channel and p-channel devices can be carried out by sharing the n.sup.+ or p.sup.+ source and drain ion implantation mask. This approach provides maximum flexibility in designing optimum n.sup.- and p.sup.- channel LDD MOSFETs without using any additional mask steps other than the conventional CMOS mask levels. This process is also compatible with self-aligned silicide process.
    Type: Grant
    Filed: June 30, 1987
    Date of Patent: June 27, 1989
    Assignee: Hewlett-Packard Company
    Inventors: Kuang Y. Chiu, Fu-Chieh Hsu
  • Patent number: 4398992
    Abstract: A method for local oxideation of a semiconductor using only conventional large scale integration (LSI) fabrication techniques is provided which results in an oxide layer without the formation of the so-called "bird's beak" structure and no process or structure induced defects. On a semiconductor substrate a mold for oxide is made by forming on the substrate, a trench with sidewalls extending upward to a localized mesa region of the substrate. The sidewalls of the mesa, the localized plateau and a distance out from the sidewalls of the mesa to a desired distance out from the sidewalls are covered by a masking layer capable of preventing oxideation of the underlying substrate. The unmasked portion of the mold is oxidized to produce a localized oxide layer which is substantially free of any "bird's beak" structure.
    Type: Grant
    Filed: May 20, 1982
    Date of Patent: August 16, 1983
    Assignee: Hewlett-Packard Company
    Inventors: Robert C. Y. Fang, Kuang Y. Chiu