Patents by Inventor Kuei-Jen Chang

Kuei-Jen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120311928
    Abstract: A container for growing plant includes a main body, a seed coating and at least a seed. The main body is composed of a biodegradable plastic material and has a seed portion. The seed coating is composed of the biodegradable plastic material and is disposed in the seed portion. The at least a seed is sealed in the seed portion of the main body through the seed coating. After a user uses up a content in the container for growing plant, the waste container can be buried into the soil to be biodegraded by the microorganism in the soil so that the seed inside the container is contacted with the air, the water and the soil to germinates, thereby growing the valuable plant.
    Type: Application
    Filed: June 13, 2011
    Publication date: December 13, 2012
    Applicant: HAIR O'RIGHT INTERNATIONAL CORPORATION
    Inventors: WANG-PING KO, Shiue-Chiau Liu, Kuei-Jen Chang
  • Patent number: 6908813
    Abstract: A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of “write disturb”, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well-controlled dimensions and well-defined shapes through a judicious use of a fully wet etch technique, including main-etch and over-etch. The use of a phosphoric acid solution in combination with sulfuric acid+hydrogen peroxide widens the process window from a few seconds to several minutes so that the small-dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In the first embodiment phosphoric solution is used both for main-etch and for over-etch. In the second embodiment, phosphoric solution is used for main-etch only, while the sulfuric+hydrogen peroxide solution is used as an over-etch in forming the tiny silicon nitride spacers of the invention.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: June 21, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Hsin Liu, Kuei-Jen Chang, Tsung-Chi Hsieh, Yuan-Ko Hwang, Shih Chiung Chen
  • Publication number: 20040203205
    Abstract: A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of “write disturb”, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well-controlled dimensions and well-defined shapes through a judicious use of a fully wet etch technique, including main-etch and over-etch. The use of a phosphoric acid solution in combination with sulfuric acid+hydrogen peroxide widens the process window from a few seconds to several minutes so that the small-dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In the first embodiment phosphoric solution is used both for main-etch and for over-etch. In the second embodiment, phosphoric solution is used for main-etch only, while the sulfuric+hydrogen peroxide solution is used as an over-etch in forming the tiny silicon nitride spacers of the invention.
    Type: Application
    Filed: April 9, 2003
    Publication date: October 14, 2004
    Applicant: Taiwan Semicondutor Manufacturing Co.
    Inventors: Hung-Hsin Liu, Kuei-Jen Chang, Tsung-Chi Hsieh, Yuan-Ko Hwang, Shih Chiung Chen
  • Patent number: 6723654
    Abstract: A method for in-situ descum/hot bake/dry etch a polyimide photoresist layer and a passivation layer in a singe process chamber is disclosed. A process chamber that can be used for conducting in-situ a descum, a hot bake and a dry etch process sequentially in the same chamber is also disclosed. In the method, a process chamber equipped with a wafer platform and a wafer backside heating and cooling device is first provided, followed by the step of positioning a wafer that has a passivation layer and a patterned polyimide photoresist layer on top of the platform. An oxygen plasma is then generated in the chamber cavity to conduct a descum process, followed by flowing a heated inert gas onto a backside of the wafer to conduct a hot bake process. A cooling inert gas is then flown onto the wafer backside and an etchant gas is flown into the chamber to conduct a dry etch process for forming a via opening in the wafer.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: April 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Kuei-Jen Chang, Yuan-Ko Hwang, Juei-Wen Lin, Jen-Yung Tseng
  • Patent number: 6489227
    Abstract: A process for creating a fuse structure opening in a stack of materials comprised with overlying dielectric layers, and comprised with an underlying polysilicon layer, to expose a conductive fuse structure, has been developed. The process initiates with a dry etching procedure used to create an initial fuse structure opening in the dielectric layers, using a photoresist shape as an etch mask. Subsequent removal of the photoresist shape results in the completion of the fuse structure opening via in situ etching of the polysilicon layer exposed in the initial fuse structure opening. The isotropic wet etch procedure used for photoresist removal and in situ patterning of polysilicon, avoids polysilicon spacer formation on the sides of the conductive fuse structure, which would have been present with the use of an all dry etch procedure. In addition the wet etch procedure selectively terminates on a thin silicon oxide layer, located on the underlying conductive fuse structure.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: December 3, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tsung-Chi Hsieh, Yuan-Ko Hwang, Juei-Wen Lin, Kuei-Jen Chang
  • Publication number: 20020139775
    Abstract: A method for in-situ descum/hot bake/dry etch a polyimide photoresist layer and a passivation layer in a singe process chamber is disclosed. A process chamber that can be used for conducting in-situ a descum, a hot bake and a dry etch process sequentially in the same chamber is also disclosed. In the method, a process chamber equipped with a wafer platform and a wafer backside heating and cooling device is first provided, followed by the step of positioning a wafer that has a passivation layer and a patterned polyimide photoresist layer on top of the platform. An oxygen plasma is then generated in the chamber cavity to conduct a descum process, followed by flowing a heated inert gas onto a backside of the wafer to conduct a hot bake process. A cooling inert gas is then flown onto the wafer backside and an etchant gas is flown into the chamber to conduct a dry etch process for forming a via opening in the wafer.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 3, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Kuei-Jen Chang, Yuan-Ko Hwang, Juei-Wen Lin, Jen-Yung Tseng
  • Patent number: 6320269
    Abstract: A protective tape is applied to the device side of a wafer (to protect it during an operation to grind the back side of the wafer) after the surface has been prepared to present only sloping surfaces to the tape. This profile prevents the otherwise sharp edges of the holes for the bonding pads from cutting into the adhesive of the tape and causing adhesive particles to remain on the wafer surface after the tape has been removed. Particles of resist can interfere with attaching wires to the bonding pads. The tape receiving surface of the wafer is commonly formed by a passivation layer and by bonding pad sites that are exposed through holes in the passivation layer. These sloping profiles can be formed by giving a sloping profile to the holes in the photoresist before the holes are etched. Alternatively the holes can be etched suitably wider at the top than at the bottom.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: November 20, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Sen-Fu Chen, Kuei-Jen Chang
  • Patent number: D695118
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: December 10, 2013
    Assignee: Hair O'Right International Corporation
    Inventors: Wang-Ping Ko, Shiue-Chiau Liu, Kuei-Jen Chang