Patents by Inventor Kuei-Shun Chen

Kuei-Shun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making a structure
    Patent number: 9466528
    Abstract: A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: October 11, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei-Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
  • Dummy gate structure and methods thereof
    Patent number: 9431513
    Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chiang Mu-Chi, Chao-Cheng Chen
  • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20160240430
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask (HM) layer over a material layer, forming a first trench in the HM layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the HM layer. The first patterned resist layer has a first opening and a second opening a second direction. The first opening overlaps with the first trench in a middle portion of the first trench and the second opening overlaps with the first trench at an end portion of the first trench. The method also includes etching the HM layer through the first patterned resist layer to form a second trench and a third trench in the HM layer and forming a first feature to fill in a section of the first trench between the second trench and the third trench.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Method of fabricating semiconductor device with reduced trench distortions
    Patent number: 9418868
    Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Method of fabricating semiconductor device
    Patent number: 9412649
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask (HM) layer over a material layer, forming a first trench in the HM layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the HM layer. The first patterned resist layer has a first opening and a second opening a second direction. The first opening overlaps with the first trench in a middle portion of the first trench and the second opening overlaps with the first trench at an end portion of the first trench. The method also includes etching the HM layer through the first patterned resist layer to form a second trench and a third trench in the HM layer and forming a first feature to fill in a section of the first trench between the second trench and the third trench.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication
    Patent number: 9366969
    Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Kuei Shun Chen, Norman Chen, Vencent Chang, Chin-Hsiang Lin
  • EXPOSURE METHOD OF WAFER SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND EXPOSURE TOOL
    Publication number: 20160124323
    Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
    Type: Application
    Filed: May 7, 2015
    Publication date: May 5, 2016
    Inventors: Hsueh-Yi CHUNG, Yung-Cheng CHEN, Fei-Gwo TSAI, Chi-Hung LIAO, Shih-Chi FU, Wei-Ti HSU, Jui-Ping CHUANG, Tzong-Sheng CHANG, Kuei-Shun CHEN, Meng-Wei CHEN
  • DUMMY GATE STRUCTURE AND METHODS THEREOF
    Publication number: 20160093715
    Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 31, 2016
    Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chiang Mu-Chi, Chao-Cheng Chen
  • Method for etching an ultra thin film
    Patent number: 9281205
    Abstract: A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Kuei-Shun Chen, Shang-Wern Chang, Chih-Yang Yeh
  • Lithography Process and System with Enhanced Overlay Quality
    Publication number: 20160062250
    Abstract: The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventors: Chi-Cheng Hung, Wei-Liang Lin, Yung-Sung Yen, Chun-Kuang Chen, Ru-Gun Liu, Tsai-Sheng Gau, Tzung-Chi Fu, Ming-Sen Tung, Fu-Jye Liang, Li-Jui Chen, Meng-Wei Chen, Kuei-Shun Chen
  • Method for making a lithography mask
    Patent number: 9274414
    Abstract: A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lun Liu, Chia-Chu Liu, Kuei-Shun Chen, Chung-Ming Wang, Chie-Chieh Lin
  • METHOD FOR REMOVING SEMICONDUCTOR FINS USING ALTERNATING MASKS
    Publication number: 20160042964
    Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.
    Type: Application
    Filed: October 23, 2015
    Publication date: February 11, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Chun LO, Min-Hung CHENG, Hsiao-Wei SU, Jeng-Shiun HO, Ching-Che TSAI, Cheng-Cheng KUO, Hua-Tai LIN, Chia-Chu LIU, Kuei-Shun CHEN
  • SEMICONDUCTOR DEVICE WITH BIASED FEATURE
    Publication number: 20150357460
    Abstract: A transistor including a gate structure with a first portion and a second portion; the first and second portions each have a first edge and an opposing second edge that are substantially collinear. The gate structure also includes an offset portion interposing the first portion and the second portion. The offset portion has a third edge and an opposing fourth edge. The third edge and the fourth edge are non-collinear with the first and second edges of the first and second portions of the gate structure. For example, the offset portion is offset or shifted from the first and second portions.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 10, 2015
    Inventors: Chia-Chu Liu, Min-Chang Liang, Mu-Chi Chiang, Kuei-Shun Chen
  • Method for removing semiconductor fins using alternating masks
    Patent number: 9184101
    Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chun Lo, Min-Hung Cheng, Hsiao-Wei Su, Jeng-Shiun Ho, Ching-Che Tsai, Cheng-Cheng Kuo, Hua-Tai Lin, Chia-Chu Liu, Kuei-Shun Chen
  • Controlling Gate Formation for High Density Cell Layout
    Publication number: 20150318367
    Abstract: Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a substrate having a first active region, a second active region, and an insulating region separating the first and the second active regions. The structure further includes a vertical gate structure extending over the first and the second active regions and the insulating region, and a horizontal gate structure extending over the insulating region between the first and the second active regions.
    Type: Application
    Filed: June 26, 2015
    Publication date: November 5, 2015
    Inventors: Harry Hak-Lay Chuang, Bao-Ru Young, Kuei Shun Chen, Cheng-Cheng Kuo, Chia-Chu Liu, Tsung-Chieh Tsai, Yuh-Jier Mii
  • Enhanced FinFET process overlay mark
    Patent number: 9129974
    Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Hsieh, Chi-Kang Chang, Chia-Chu Liu, Meng-Wei Chen, Kuei-Shun Chen
  • METHOD AND STRUCTURE FOR GAP FILLING IMPROVEMENT
    Publication number: 20150214226
    Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Hao SU, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
  • Contrast enhancing exposure system and method for use in semiconductor fabrication
    Patent number: 9091923
    Abstract: Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators (“PAGs”) and photobase generators (“PBGs”), is described.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: George Liu, Vencent Chang, Norman Chen, Kuei Shun Chen, Chin-Hsiang Lin
  • Controlling gate formation for high density cell layout
    Patent number: 9070623
    Abstract: Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: June 30, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Kuei Shun Chen, Cheng Cheng Kuo, George Liu, Tsung-Chieh Tsai, Yuhi-Jier Mii
  • Semiconductor device with biased feature
    Patent number: 9059001
    Abstract: A method of fabricating a semiconductor device includes forming a plurality of line element on a provided substrate. The plurality of line elements includes a first line element having a first region having a first width and a biased region having a second width. The second width different than the first width. Spacer elements are then formed abutting sidewalls of each of the plurality of line elements including the biased region where the spacer elements may be shifted. After forming the spacer elements, the plurality of line elements from the substrate are removed from the substrate. An underlying layer is etched using the spacer elements after removing the plurality of line elements.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: June 16, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Minchang Liang, Mu-Chi Chiang, Kuei Shun Chen