Patents by Inventor Kuei-Ya Chuang
Kuei-Ya Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11758720Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.Type: GrantFiled: December 7, 2022Date of Patent: September 12, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Min Hung, Ping-Chia Shih, Che-Hao Kuo, Kuei-Ya Chuang, Ssu-Yin Liu, Po-Hsien Chen, Wan-Chun Liao
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Publication number: 20230103976Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.Type: ApplicationFiled: December 7, 2022Publication date: April 6, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Min Hung, Ping-Chia Shih, Che-Hao Kuo, Kuei-Ya Chuang, Ssu-Yin Liu, Po-Hsien Chen, Wan-Chun Liao
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Patent number: 11616069Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.Type: GrantFiled: October 19, 2020Date of Patent: March 28, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ping-Chia Shih, Kuei-Ya Chuang, Chuang-Hsin Chueh, Ming-Che Tsai, Wen-Lin Wang, Yi-Chun Teng, Ssu-Yin Liu, Wan-Chun Liao
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Patent number: 11552088Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.Type: GrantFiled: March 11, 2021Date of Patent: January 10, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Min Hung, Ping-Chia Shih, Che-Hao Kuo, Kuei-Ya Chuang, Ssu-Yin Liu, Po-Hsien Chen, Wan-Chun Liao
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Publication number: 20220293615Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Chia-Min Hung, Ping-Chia Shih, Che-Hao Kuo, Kuei-Ya Chuang, Ssu-Yin Liu, Po-Hsien Chen, Wan-Chun Liao
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Patent number: 11282799Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.Type: GrantFiled: January 14, 2020Date of Patent: March 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Lin Wang, Ping-Chia Shih, Ming-Che Tsai, Kuei-Ya Chuang, Yi-Chun Teng, Po-Hsien Chen, Wan-Chun Liao
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Publication number: 20220077166Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.Type: ApplicationFiled: October 19, 2020Publication date: March 10, 2022Inventors: Ping-Chia SHIH, Kuei-Ya CHUANG, Chuang-Hsin CHUEH, Ming-Che TSAI, Wen-Lin WANG, Yi-Chun TENG, Ssu-Yin LIU, Wan-Chun LIAO
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Publication number: 20210217708Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.Type: ApplicationFiled: January 14, 2020Publication date: July 15, 2021Inventors: Wen-Lin Wang, Ping-Chia Shih, Ming-Che Tsai, Kuei-Ya Chuang, Yi-Chun Teng, Po-Hsien Chen, Wan-Chun Liao