Abstract: An image sensor includes a substrate, at least an optical device, at least a dielectric layer, and at least a wave-guide tube disposed upon the optical device. The wave-guide tube has an optical barrier disposed on a sidewall thereof and a filter layer filled in the wave-guide tube. The structure of the wave-guide tube has the advantages of shortening light path, focusing, and preventing undesirable crosstalk effect between different optical devices.

Abstract: An image sensor includes a substrate, at least an optical device, at least a dielectric layer, and at least a wave-guide tube disposed upon the optical device. The wave-guide tube has an optical barrier disposed on a sidewall thereof and a filter layer filled in the wave-guide tube. The structure of the wave-guide tube has the advantages of shortening light path, focusing, and preventing undesirable crosstalk effect between different optical devices.

Abstract: In the present invention, setting apparatus for semiconductor equipment with multitude of chambers comprises a plurality of input devices coupled to a controlling system of the semiconductor equipment. The input devices are used for setting a maintain status of said chambers whereby said chambers can be available for a test process. A method for setting a plurality of statuses for a plurality of chambers in semiconductor equipment comprises setting a plurality of maintain statuses for the chambers and executing a plurality of test process in the chambers in the maintain statuses. To be specific, the setting step can simultaneously set an on-line status for each the chamber and the maintain status for other the chamber.

Abstract: In the present invention, setting apparatus for semiconductor equipment with multitude of chambers comprises a plurality of input devices coupled to a controlling system of the semiconductor equipment. The input devices are used for setting a maintain status of said chambers whereby said chambers can be available for a test process. A method for setting a plurality of statuses for a plurality of chambers in semiconductor equipment comprises setting a plurality of maintain statuses for the chambers and executing a plurality of test process in the chambers in the maintain statuses. To be specific, the setting step can simultaneously set an on-line status for each the chamber and the maintain status for other the chamber.

Abstract: An integrated circuit (IC) fabrication method is provided for fabricating a conductive plug, such as a contact plug or a via plug, with a low junction resistance in an integrated circuit. This method is characterized by the inclusion of a preliminary doping process to form a doped region in the exposed area through the contact opening or via opening. By conventional method, the exposed area would be formed with an undesired oxide layer or laid with undesired reactant remnants after the etching process for forming the contact opening or via opening. When being subjected to a high temperature during the subsequent deposition process, the dopant atoms in the doped region diffuse into these undesired insulative matters, thereby reducing the junction resistance of the resulting contact or via plug.

Abstract: A method of fabricating a coronary-type capacitor in integrated circuit is provided, which method helps increase the capacitance of the capacitor by forming the electrode of the capacitor with a coronary-like shape that is relatively large in surface area. In this method, a stacked structure of doped polysilicon layers and HSG polysilcon layers are formed in an alternating manner, which is then selectively removed to form a void portion. A heat-treatment process is then performed on the wafer at a temperature of about 600-700° C. to cause the impurity ions in the doped polysilicon layers to be activated and evenly diffused over the inside of the doped polysilicon layers. Finally, a selective etching process is performed with an etchant that can react with polysilicon at a faster etching rate than with HSG polysilcon so as to cause the sidewalls of the doped polysilicon layers to be more recessed than the sidewalls of the HSG polysilcon layers.

Abstract: An apparatus and a method of forming a thick polysilicon layer are provided. An additional pipeline is introduced into a chamber that is used for depositing polysilicon layers. A thin silicon dioxide film is formed using oxygen after forming a first doped polysilicon layer with a constant thickness. Then a second doped polysilicon layer with a constant thickness is deposited on the thin silicon dioxide layer. The steps described above are repeated until a desired thickness is attained.

Abstract: The method of the invention starts with forming a mask on a blank wafer, wherein the mask contains a number of openings that expose a portion of the wafer. By performing a wet oxidation process, field oxide is formed on the exposed surface of the wafer. The wafer surface is then become ragged after the mask and the field oxide are removed. In order to further increase the surface area of a dummy wafer, an etching process is performed on the ragged surface after a hemispherical grained layer is formed on the ragged surface.

Abstract: A method for fabricating gate oxide includes a dilute wet oxidation process with additional nitrogen and moisture and an annealing process with a nitrogen base gas, wherein the volume of additional nitrogen is about 6-12 times of the volume of the additional moisture. The method according to the invention improves the electrical quality of the gate oxide by raising the Q.sub.bd and by reducing the leakage current of the gate oxide.

Abstract: A method for fabricating a field effect transistor (FET) with a T-like gate structure includes forming a silicon nitride layer over a silicon substrate and patterning it to form an opening that exposes the substrate. A dielectric layer is formed on a lower portion of each side-wall of the opening so that the opening has a T-like free space. A doped polysilicon layer fills the T-like free space through only one deposition. After performing a planarization on the doped polysilicon layer, a titanium metal layer is formed over the substrate. A self-aligned titanium silicide is formed over the substrate other than the dielectric layer surface through a rapid thermal process (RTP). A selective etching process is performed to remove the remaining titanium metal layer. After removing the dielectric layer a RTP is performed again to reform the crystal structure of the titanium silicide layer so as to reduce its resistance. A T-like gate structure is formed.

Abstract: A method for fabricating a capacitor including a storage capacitor of a dynamic random access memory (DRAM) starts with forming a dielectric layer and then a mask on a provided substrate, wherein the provided substrate contains a pre-formed field effect transistor (FET). By patterning the dielectric layer, a contact window is formed to expose the source/drain regions on the provided substrate. Then, a conducting layer is formed to cover the mask and fill the contact window, wherein the conducting layer is electrically connected to the source/drain region. A hemispherical-grained silicon (HSG) layer is formed on the conducting layer, wherein the silicon grains are respectively surrounded by spacers formed in a follow-up process. The HSG layer and a portion of the conducting layer are removed by performing an anisotropic etching process that uses the spacers as masks. The remains of the conducting layer, a multi-micro-cylinder structure, serves as the storage electrode of a capacitor.

Abstract: A method for determining the impurity concentration of impurity-doped polysilicon layers in semiconductor wafers is provided. Through experiments, it is found that the reflectivity of an impurity-doped polysilicon layer is nearly a regular function of the impurity concentration thereof. Accordingly, an impurity-doped polysilicon layer having an unknown impurity concentration can be determined by first measuring the reflectivity thereof by illuminating the impurity-doped polysilicon layer with light, and then using mapping transformation to find the corresponding value of impurity concentration of the impurity-doped polysilicon layer. This method can be used instead of the conventional thermal wave method that often result in having to discard the wafers due to the incapability of reliably determining the impurity concentration of the polysilicon layers formed on the semiconductor wafers.

Abstract: A method for fabricating gate oxide includes a dilute wet oxidation process with additional nitrogen and moisture and an annealing process with a nitrogen base gas, wherein the volume of additional nitrogen is about 6-12 6-20 times of the volume of the additional moisture. The method according to the invention improves the electrical quality of the gate oxide by raising the Qbd and by reducing the leakage current of the gate oxide.