Abstract: A method for designing and constructing a thin programmable dynamic credential card is disclosed. The thin programmable dynamic credential card may comprise multiple layers, including a top surface layer containing an opening through which a graphical display system below the top surface layer can be viewed. The graphical display system is configured to present at least one coded image. The at least one coded image is determined based at least in part on context data associated with a context of the programmable credential card.

Abstract: A method for designing and constructing a thin programmable dynamic credential card is disclosed. The thin programmable dynamic credential card may comprise multiple layers, including a top surface layer containing an opening through which a graphical display system below the top surface layer can be viewed. The graphical display system is configured to present at least one coded image. The at least one coded image is determined based at least in part on context data associated with a context of the programmable credential card.

Abstract: A method for designing and constructing a thin programmable dynamic credential card is disclosed. The thin programmable dynamic credential card may comprise multiple layers, including a top surface layer containing an opening through which a graphical display system below the top surface layer can be viewed. The graphical display system is configured to present at least one coded image. The at least one coded image is determined based at least in part on context data associated with a context of the programmable credential card.

Abstract: A method for designing and constructing a thin programmable dynamic credential card is disclosed. The thin programmable dynamic credential card may comprise nine different layers carefully constructed to house a battery, a processor, a wireless communication system, a solenoid coil, a graphical display, input buttons, and other electrical components all within the thin form factor of a credit card.

Abstract: Conventional magnetic stripe cards are encoded with static magnetic patterns. To act like many different magnetic stripe cards, a programmable dynamic magnetic stripe card disclosed. The programmable dynamic magnetic stripe card includes a solenoid coil for generating a magnetic field and solenoid coil driver circuitry for driving the solenoid coil to generate a magnetic field. To improve the quality of the magnetic field generated, a biasing magnet is placed adjacent to the solenoid coil.

Abstract: A method for designing and constructing a thin programmable dynamic credential card is disclosed. The thin programmable dynamic credential card may comprise nine different layers carefully constructed to house a battery, a processor, a wireless communication system, a solenoid coil, a graphical display, input buttons, and other electrical components all within the thin form factor of a credit card.

Abstract: Conventional magnetic stripe cards are encoded with static magnetic patterns. To act like many different magnetic stripe cards, a programmable dynamic magnetic stripe card disclosed. The programmable dynamic magnetic stripe card includes a solenoid coil for generating a magnetic field and solenoid coil driver circuitry for driving the solenoid coil to generate a magnetic field. To improve the quality of the magnetic field generated, a biasing magnet is placed adjacent to the solenoid coil.

Abstract: A dynamic credential card system for interoperating with multiple different point-of-sale systems is disclosed. The system comprises three computer systems: a dynamic digital value transfer system operating on a server, a dynamic digital value transfer application operating on a mobile digital device, and a small programmable dynamic credential card system. The dynamic digital value transfer system interoperates with third party payment systems and communicates with the dynamic digital value transfer application. The dynamic digital value transfer application communicates with the small programmable dynamic credential card system. The small programmable dynamic credential card system has at least one Point-of-Sale communication system for communicating with retail Point-Of-Sale terminals.

Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

Abstract: Methods and structures for a double-sided semiconductor structure using through-silicon vias (TSVs) are disclosed. The double-sided structure has functional circuits on both the front and back sides, interconnected by one or more TSVs. In some embodiments, multiple double-sided structures are combined to create 3D semiconductor structures with increased circuit density.

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

Abstract: One illustrative method disclosed herein includes forming first and second FinFET devices in and above a first region and a second region of a semiconducting substrate, respectively, performing a first ion implantation process through a patterned mask layer to implant nitrogen into the second region, removing the patterned mask layer, performing a second ion implantation process to implant oxygen atoms into both the first and second regions, performing a heating process to form a layer of insulating material at least in the first region and performing at least one etching process to define at least one first fin in the first region and to define at least one second fin in the second region, the second fin being taller than the first fin.

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.