Patents by Inventor Kumar Ganapathy
Kumar Ganapathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10193878Abstract: In general, in one aspect, embodiments relate to receiving, by a system comprising one or more network devices, a first client authentication information comprising a first indication that a first client device was successfully authenticated by a first authentication server based on credentials provided by the first client device, and forwarding, by the system, the first client authentication information to a second authentication server without determining that the client device was already successfully authenticated by the first authentication server based on the credentials provided by the first client device. The operations further include receiving, by the system from the second authentication server, a second indication that the first client device was successfully authenticated, and based on the second indication received by the system from the second authentication server, granting, by the system, network access to the first client device.Type: GrantFiled: October 31, 2013Date of Patent: January 29, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Venkatraju Tumkur Venkatanaranappa, Rajesh Kumar Ganapathy Achari, Anoop Kumaran Nair, Santhosh Cheeniyil
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Patent number: 10156890Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.Type: GrantFiled: April 6, 2016Date of Patent: December 18, 2018Assignee: VIRIDENT SYSTEMS, LLCInventors: Vijay Karamcheti, Kenneth Alan Okin, Kumar Ganapathy
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Patent number: 9984012Abstract: A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.Type: GrantFiled: September 28, 2014Date of Patent: May 29, 2018Assignee: VIRIDENT SYSTEMS, LLCInventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
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Publication number: 20180121379Abstract: A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.Type: ApplicationFiled: September 28, 2014Publication date: May 3, 2018Inventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
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Patent number: 9866522Abstract: The present disclosure discloses a method and a network device for controlling DHCP pool exhaustion in dynamic network environments. Specifically, a network device determines that a client device is assigned an Internet Protocol (IP) address by a DHCP server. The network device detects that the client device is disconnected from a network associated with the IP address, for example, by receiving a de-association message from the client device; determining that a session or an entry corresponding to the client device has timed out; determining that the client device has failed to respond to one or more messages transmitted to the client device; determining that the client device has connected to another network different than said network; etc. In response, the network device then generates a DHCP release message on behalf of the client device, and transmits the DHCP release message to the DHCP server.Type: GrantFiled: July 29, 2014Date of Patent: January 9, 2018Assignee: ARUBA NETWORKS, INC.Inventors: Avignan Chatterjee, Rajesh Kumar Ganapathy Achari, Srinivasan Jayarajan, Harsha Nagaraja, Anoop Kumaran Nair, Venkatesh Ramachandran, Isaac Theogaraj, Venkatraju Venkatanaranappa
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Patent number: 9836409Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.Type: GrantFiled: January 6, 2016Date of Patent: December 5, 2017Assignee: VIRIDENT SYSTEMS, LLCInventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 9824193Abstract: The present disclosure discloses a method and network device for using mobile devices with validated user network identity as physical identity proof. Responsive to successfully authenticating a client device for network access, a system generates a network credential for the client device and transmits the network credential to the client device. Further, the system detects that the client device is within a range of a short range wireless device that is associated with a particular physical action. Consequently, the system validates the network credential that the client device possesses. Based on the network credential, the system determines that the client device has permissions for performing the particular physical action, and causes performance of the particular physical action.Type: GrantFiled: July 29, 2014Date of Patent: November 21, 2017Assignee: ARUBA NETWORKS, INC.Inventors: Rajesh Kumar Ganapathy Achari, Anoop Kumaran Nair, Venkatesh Ramachandran, Venkatraju Venkatanaranappa
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Patent number: 9767867Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.Type: GrantFiled: September 2, 2013Date of Patent: September 19, 2017Assignee: Virident Systems, Inc.Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Publication number: 20170220461Abstract: An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Inventors: Vijay KARAMCHETI, Kumar GANAPATHY, Kenneth Alan OKIN, Rajesh PAREKH
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Patent number: 9672158Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.Type: GrantFiled: January 7, 2016Date of Patent: June 6, 2017Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 9626290Abstract: An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.Type: GrantFiled: September 2, 2014Date of Patent: April 18, 2017Assignee: Virident Systems, LLCInventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
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Patent number: 9590972Abstract: In general, in one aspect, embodiments relate to receiving, by a system of one or more network devices from a client device, a request to access one or more applications, determining, by the system, that the client device has already been authenticated to access a network, and based on determining that the client device has already been authenticated to access the network, causing authenticating of the client device for accessing the one or more applications.Type: GrantFiled: October 31, 2013Date of Patent: March 7, 2017Assignee: ARUBA NETWORKS, INC.Inventors: Venkatraju Tumkur Venkatanaranappa, Rajesh Kumar Ganapathy Achari, Anoop Kumaran Nair, Santhosh Cheeniyil
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Patent number: 9536609Abstract: A memory module is provided. In one example, the memory module includes a printed circuit board with one or more connectors, and a plurality of multi-chip packaged integrated circuit parts mounted to the printed circuit board. Each of the plurality of multi-chip packaged integrated circuit parts includes an integrated circuit package including a slave memory controller (SMC) die and one or more pairs of (1) a spacer under the slave memory controller die and (2) a flash memory die under the spacer. Each flash memory die is larger than each spacer to provide an opening into a perimeter of the flash memory die to which electrical connections may be made.Type: GrantFiled: July 27, 2015Date of Patent: January 3, 2017Assignee: Virident Systems, Inc.Inventors: Vijay Karamcheti, Kumar Ganapathy
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Patent number: 9513695Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.Type: GrantFiled: July 26, 2013Date of Patent: December 6, 2016Assignee: Virident Systems, Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy
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Publication number: 20160342195Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.Type: ApplicationFiled: April 6, 2016Publication date: November 24, 2016Inventors: Vijay Karamcheti, Kenneth Alan Okin, Kumar Ganapathy
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Publication number: 20160117258Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.Type: ApplicationFiled: January 6, 2016Publication date: April 28, 2016Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Publication number: 20160117131Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.Type: ApplicationFiled: January 7, 2016Publication date: April 28, 2016Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Publication number: 20160092384Abstract: A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.Type: ApplicationFiled: September 28, 2014Publication date: March 31, 2016Inventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
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Patent number: 9262333Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.Type: GrantFiled: October 7, 2013Date of Patent: February 16, 2016Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 9262334Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.Type: GrantFiled: July 14, 2014Date of Patent: February 16, 2016Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh