Patents by Inventor Kumar Rangarajan

Kumar Rangarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948259
    Abstract: Embodiments of the present invention provide a system for processing and integrating real-time environment instances into virtual reality live streams. The system is configured for determining that a user is accessing a virtual environment, capturing real-time environment instance associated with the virtual environment via one or more capturing devices, creating a neutral environment template based on processing the real-time environment instance, embedding one or more preferential objects associated with the user into the neutral environment template to generate a preferred environment template, and instantaneously integrating the preferred environment template into a virtual reality live stream associated with the virtual environment in real-time.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 2, 2024
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Suryanarayan Parthasarathi Chakravarthi, Pritika Bhatia, Harshit Bhatt, Saisrikanth Chitty, Neha Jain, Mithun Kumar, Madhumitha Swaminathan Rangarajan
  • Patent number: 11888791
    Abstract: Systems and processes for providing response suggestions are provided. In one example process, a textual representation of a message is received. Based on the textual representation of the message, one or more response categories and a predetermined number of suggested inputs corresponding to each of the one of more response categories are obtained. Based on the predetermined number of suggested inputs corresponding to each of the one of more response categories, one or more suggested inputs for each of the one or more response categories are determined. The one or more suggested inputs are provided as response suggestions to the message.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: January 30, 2024
    Assignee: Apple Inc.
    Inventors: Vojtech Jina, Seth J. Hildick-Smith, Peter M. Kirby, Vivek Kumar Rangarajan Sridhar
  • Patent number: 11880454
    Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: January 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Kumar Rangarajan, Dipti Ranjan Pal, Keith Alan Bowman, Srinivas Turaga, Ateesh Deepankar De, Shih-Hsin Jason Hu, Chandan Agarwalla
  • Patent number: 11630694
    Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: April 18, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Vijayakumar Ashok Dibbad, Bharat Kumar Rangarajan, Prashanth Kumar Kakkireni, Srinivas Turaga
  • Patent number: 11604505
    Abstract: Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 14, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Kumar Rangarajan, Rajesh Arimilli, Rengarajan Ragavan
  • Publication number: 20230075113
    Abstract: A system, method and computer-readable storage devices for providing unsupervised normalization of noisy text using distributed representation of words. The system receives, from a social media forum, a word having a non-canonical spelling in a first language. The system determines a context of the word in the social media forum, identifies the word in a vector space model, and selects an “n-best” vector paths in the vector space model, where the n-best vector paths are neighbors to the vector space path based on the context and the non-canonical spelling. The system can then select, based on a similarity cost, a best path from the n-best vector paths and identify a word associated with the best path as the canonical version.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Inventor: Vivek Kumar Rangarajan Sridhar
  • Patent number: 11507174
    Abstract: In certain aspects, a tag memory comprises a plurality of non-configurable tag columns configured to be powered on during a normal operation; and a plurality of configurable tag columns, wherein a first portion of the plurality of configurable tag columns is configured to be powered off during the normal operation and a second portion of the plurality of configurable tag columns is configured to be powered on during the normal operation.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: November 22, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Kumar Rangarajan, Srinivas Turaga
  • Publication number: 20220365580
    Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.
    Type: Application
    Filed: May 17, 2021
    Publication date: November 17, 2022
    Inventors: VIJAYAKUMAR ASHOK DIBBAD, Bharat Kumar RANGARAJAN, Dipti Ranjan PAL, Keith Alan BOWMAN, Matthew SEVERSON, Gordon LEE
  • Patent number: 11501066
    Abstract: A system, method and computer-readable storage devices for providing unsupervised normalization of noisy text using distributed representation of words. The system receives, from a social media forum, a word having a non-canonical spelling in a first language. The system determines a context of the word in the social media forum, identifies the word in a vector space model, and selects an “n-best” vector paths in the vector space model, where the n-best vector paths are neighbors to the vector space path based on the context and the non-canonical spelling. The system can then select, based on a similarity cost, a best path from the n-best vector paths and identify a word associated with the best path as the canonical version.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 15, 2022
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Vivek Kumar Rangarajan Sridhar
  • Patent number: 11493980
    Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: November 8, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Vijayakumar Ashok Dibbad, Bharat Kumar Rangarajan, Dipti Ranjan Pal, Keith Alan Bowman, Matthew Severson, Gordon Lee
  • Patent number: 11493986
    Abstract: Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.
    Type: Grant
    Filed: December 22, 2019
    Date of Patent: November 8, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Kumar Rangarajan, Rajesh Arimilli, Srinivas Turaga
  • Publication number: 20220222112
    Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 14, 2022
    Inventors: Vijayakumar Ashok DIBBAD, Bharat Kumar RANGARAJAN, Prashanth Kumar KAKKIRENI, Srinivas TURAGA
  • Patent number: 11386266
    Abstract: The present disclosure generally relates to text correction and generating text correction models. In an example process for text correction, text input is received. In response to receiving the text input, a text string corresponding to the text input is displayed. The text string is represented by a token sequence. The process determines whether an end of the token sequence corresponds to a text boundary. In accordance with a determination that the end of the token sequence corresponds to a text boundary, the process determines, based on a context state of the token sequence, one or more textual errors at one or more tokens of the token sequence. An error indication for a portion of the text string corresponding to the one or more tokens is displayed.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: July 12, 2022
    Assignee: Apple Inc.
    Inventors: Douglas R. Davidson, Bishal Barman, Vivek Kumar Rangarajan Sridhar
  • Publication number: 20220206559
    Abstract: Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Bharat Kumar RANGARAJAN, Rajesh ARIMILLI, Rengarajan RAGAVAN
  • Publication number: 20220093088
    Abstract: Methods and systems for embedding natural language sentences within a highly-dimensional vector space are provided. Additionally, various applications relating to natural language processing, are provided. Such applications include digital assistants and search engines, as well as systems for classifying, sorting, organizing, and/or pairing content that are associated with natural language objects. The sentence vector embeddings encode various semantic features of the sentence. Two separate language models, arranged in a serial architecture are employed to generate a sentence vector. The first language model generates token vectors for each of the tokens included in the sentence. The token vectors are employed as inputs to the second language model. The second language model generates the sentence vector for the sentence. A sentence vector embeds the semantic context of the corresponding natural language object within the vector space.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 24, 2022
    Inventors: Vivek Kumar RANGARAJAN SRIDHAR, Barada Prasanna Acharya, Douglas Ross Davidson, Xingwen XU
  • Patent number: 11250041
    Abstract: A device implementing a system for expanded search includes a processor configured to identify plural words, and generate, for each word of the plural words, a word vector based on a proximity of the word relative to other words of the plural words, the word vector comprising plural dimensions. The processor is further configured to create a compressed word vector structure comprising clusters of subsets of the plural dimensions across the word vectors, each cluster including similar values of the respective dimensions, convert the word vectors to points on at least one plane, and partition the at least one plane into nested groupings of the points based on a threshold number of points per nested grouping. The processor is further configured to create a tree look-up structure of the nested groupings, and provide the compressed word vector structure and the tree look-up structure to a client device.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 15, 2022
    Assignee: Apple Inc.
    Inventors: Vivek Kumar Rangarajan Sridhar, Xingwen Xu, Vignesh Jagadeesh
  • Publication number: 20220021631
    Abstract: Systems and processes for providing response suggestions are provided. In one example process, a textual representation of a message is received. Based on the textual representation of the message, one or more response categories and a predetermined number of suggested inputs corresponding to each of the one of more response categories are obtained. Based on the predetermined number of suggested inputs corresponding to each of the one of more response categories, one or more suggested inputs for each of the one or more response categories are determined. The one or more suggested inputs are provided as response suggestions to the message.
    Type: Application
    Filed: October 1, 2021
    Publication date: January 20, 2022
    Inventors: Vojtech JINA, Seth J. HILDICK-SMITH, Peter M. KIRBY, Vivek Kumar RANGARAJAN SRIDHAR
  • Publication number: 20210357502
    Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Inventors: Bharat Kumar RANGARAJAN, Dipti Ranjan PAL, Keith Alan BOWMAN, Srinivas TURAGA, Ateesh Deepankar DE, Shih-Hsin Jason HU, Chandan AGARWALLA
  • Patent number: 11169593
    Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: November 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Raghavendra Srinivas, Bharat Kumar Rangarajan, Rajesh Arimilli
  • Patent number: D994340
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: August 8, 2023
    Assignee: The Gillette Company LLC
    Inventors: Christine Hallein, Dominik Langhammer, Debanjan Sengupta, Chander Swamy, Laxman Kumar Rangarajan, Karthikeyan Sokkanathan