Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.

Abstract: A digital logic device is disclosed that includes registers, SRAM, DRAM, and a processor configured to store in the registers an initial portion of a first response data to a command, and store in the SRAM the first response data. The processor is further configured to store in a lookup table the memory location and size of the first response data in the SRAM, store in the DRAM additional response data, and store in the lookup table the memory location and size of the additional response data in the DRAM. The processor is configured to receive the command from a host device, retrieve the first response data from the registers or the SRAM, and send the first response data to the host. If the command includes additional response data, the processor is configured to concurrently retrieve the additional response data from DRAM and send the additional response data to the host.

Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.

Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.

Abstract: A digital logic device is disclosed that includes registers, SRAM, DRAM, and a processor configured to store in the registers an initial portion of a first response data to a command, and store in the SRAM the first response data. The processor is further configured to store in a lookup table the memory location and size of the first response data in the SRAM, store in the DRAM additional response data, and store in the lookup table the memory location and size of the additional response data in the DRAM. The processor is configured to receive the command from a host device, retrieve the first response data from the registers or the SRAM, and send the first response data to the host. If the command includes additional response data, the processor is configured to concurrently retrieve the additional response data from DRAM and send the additional response data to the host.

Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.

Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.

Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.

Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.

Abstract: A method is described for capturing USB data traffic for a monitored device by a USB analyzer using a single USB host controller. It comprises the steps of: generating and storing an address and communication speed associated with the USB analyzer; reading a USB packet; discarding selected read packets based on the stored analyzer address and communication speed; and transmitting the remaining packets to an analysis computer.

Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation and a second packet generated by a USB analyzer are received. It is determined based at least in part on a first time associated with the first packet and a second time associated with the second packet that the class level operation has timed out. In some embodiments, an enumeration record is copied from a buffer configured to store USB data associated with a target USB device to a storage location not in the buffer, based at least in part on an indication that the enumeration record as stored in the buffer may be overwritten. In some embodiments, USB data is displayed for analysis at least in part by grouping packets not likely to be of interest differently depending on whether class level decoding is enabled.

Abstract: A method is described for capturing USB data traffic for a monitored device by a USB analyzer using a single USB host controller. It comprises the steps of: generating and storing an address and communication speed associated with the USB analyzer; reading a USB packet; discarding selected read packets based on the stored analyzer address and communication speed; and transmitting the remaining packets to an analysis computer.

Abstract: A method is described for capturing USB data traffic for a monitored device by a USB analyzer using a single USB host controller. It comprises the steps of: generating and storing an address and communication speed associated with the USB analyzer; reading a USB packet; discarding selected read packets based on the stored analyzer address and communication speed; and transmitting the remaining packets to an analysis computer.

Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation and a second packet generated by a USB analyzer are received. It is determined based at least in part on a first time associated with the first packet and a second time associated with the second packet that the class level operation has timed out. In some embodiments, an enumeration record is copied from a buffer configured to store USB data associated with a target USB device to a storage location not in the buffer, based at least in part on an indication that the enumeration record as stored in the buffer may be overwritten. In some embodiments, USB data is displayed for analysis at least in part by grouping packets not likely to be of interest differently depending on whether class level decoding is enabled.

Abstract: The Universal Serial Bus (“USB”) 2.0 Specification defines three speeds of communication for its bus, and each has its own signaling characteristics. Due to the uniqueness of each speed, PHYs must be placed in a separate mode for each signaling rate. Although USB devices may know its communication speed, a general purpose USB analyzer must be able to analyze all USB communications. Rather than force the user to manually set the operating mode of the analyzer, this invention describes circuits for automatically and reliably determining the monitored USB communication speed.

Abstract: The Universal Serial Bus (“USB”) 2.0 Specification defines three speeds of communication for its bus, and each has its own signaling characteristics. Due to the uniqueness of each speed, PHYs must be placed in a separate mode for each signaling rate. Although USB devices may know its communication speed, a general purpose USB analyzer must be able to analyze all USB communications. Rather than force the user to manually set the operating mode of the analyzer, this invention describes circuits for automatically and reliably determining the monitored USB communication speed.