Patents by Inventor Kumi Okuwada
Kumi Okuwada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7214595Abstract: A method of producing semiconductor devices is provided, which makes it possible to bury a silicon oxide without shape deterioration in device isolation trenches. The method comprises the steps of: forming an etching resistive mask over a semiconductor substrate; etching the semiconductor substrate through an opening in the etching resistive mask to form a device isolation trench; forming a coat of a silazane perhydride polymer solution over the semiconductor substrate having the device isolation trench formed therein; vaporizing a solvent from the coat and then subjecting the coat to chemical reaction to form a film of silicon oxide; removing said film of the silicon oxide leaving a residue inside said device isolation trench; and heating said silicon oxide left in said device isolation trench for densification.Type: GrantFiled: June 27, 2003Date of Patent: May 8, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Kawasaki, Satoshi Matsuda, Hisakazu Matsumori, Hidenori Shibata, Kumi Okuwada
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Publication number: 20040266131Abstract: A method of producing semiconductor devices is provided, which makes it possible to bury a silicon oxide without shape deterioration in device isolation trenches. The method comprises the steps of: forming an etching resistive mask over a semiconductor substrate; etching the semiconductor substrate through an opening in the etching resistive mask to form a device isolation trench; forming a coat of a silazane perhydride polymer solution over the semiconductor substrate having the device isolation trench formed therein; vaporizing a solvent from the coat and then subjecting the coat to chemical reaction to form a film of silicon oxide; removing said film of the silicon oxide leaving a residue inside said device isolation trench; and heating said silicon oxide left in said device isolation trench for densification.Type: ApplicationFiled: June 27, 2003Publication date: December 30, 2004Inventors: Atsuko Kawasaki, Satoshi Matsuda, Hisakazu Matsumori, Hidenori Shibata, Kumi Okuwada
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Patent number: 6750093Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: GrantFiled: December 6, 2002Date of Patent: June 15, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Publication number: 20040061157Abstract: Disclosed is a semiconductor device, comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate and comprising a lower electrode having a metallic property, an upper electrode having a metallic property and a dielectric region provided between the lower electrode and the upper electrode, the dielectric region including a first dielectric film containing silicon, oxygen and at least one element selected from hafnium and zirconium.Type: ApplicationFiled: November 26, 2002Publication date: April 1, 2004Inventors: Masahiro Kiyotoshi, Kumi Okuwada
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Patent number: 6699726Abstract: The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film.Type: GrantFiled: January 3, 2003Date of Patent: March 2, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Hidaka, Sumito Ootsuki, Hiroshi Mochizuki, Hiroyuki Kanaya, Kumi Okuwada, Tomio Katata, Norihisa Arai, Hiroyuki Takenaka
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Publication number: 20030134464Abstract: The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film.Type: ApplicationFiled: January 3, 2003Publication date: July 17, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Osamu Hidaka, Sumito Ootsuki, Hiroshi Mochizuki, Hiroyuki Kanaya, Kumi Okuwada, Tomio Katata, Norihisa Arai, Hiroyuki Takenaka
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Publication number: 20030092235Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: ApplicationFiled: December 6, 2002Publication date: May 15, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Patent number: 6521927Abstract: The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film.Type: GrantFiled: June 23, 1998Date of Patent: February 18, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Hidaka, Sumito Ootsuki, Hiroshi Mochizuki, Hiroyuki Kanaya, Kumi Okuwada, Tomio Katata, Norihisa Arai, Hiroyuki Takenaka
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Patent number: 6511877Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: GrantFiled: August 6, 2001Date of Patent: January 28, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Publication number: 20020044171Abstract: An ink-jet recording apparatus according to the present invention, which records an image onto a recording medium by flying an ink-droplet from a surface of an ink by a pressure of ultrasonic beam, is characterized by comprising ultrasonic generating element array which has a plurality of ultrasonic elements arranged in array for emitting ultrasonic beams, driving means for applying a plurality of pulses having different phases each other to converging ultrasonic beams by interfering said plurality of ultrasonic beams with each other emitted from said ultrasonic generating elements of a part of said ultrasonic generating element array, which are simultaneously driven, with sequentially shifting said ultrasonic generating elements simultaneously driven to an array direction, and converging means for converging each of said plurality of ultrasonic beams in a direction of perpendicular to the array direction.Type: ApplicationFiled: October 12, 1999Publication date: April 18, 2002Inventors: SHUZO HIRAHARA, TUTOMU SAITO, HITOSHI NAGATO, TETSURO ITAKURA, SATOSHI TAKAYAMA, HIDEKI NUKADA, SHUNSUKE HATTORI, NORIKO Y. KUDO, SHIROH SAITOH, MASAMI SUGIUCHI, YOICHI TOKAI, FIMIHIKO MURAKAMI, HISAKO TANAKA, CHIAKI TANUMA, MAMORU IZUMI, ISAO AMEMIYA, ATSUKO NAKAMURA, SEIZABUROU SHIMIZU, KUMI OKUWADA
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Publication number: 20020040988Abstract: The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film.Type: ApplicationFiled: June 23, 1998Publication date: April 11, 2002Inventors: OSAMU HIDAKA, SUMITO OOTSUKI, HIROSHI MOCHIZUKI, HIROYUKI KANAYA, KUMI OKUWADA, TOMIO KATATA, NORIHISA ARAI, HIROYUKI TAKENAKA
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Publication number: 20010051414Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: ApplicationFiled: August 6, 2001Publication date: December 13, 2001Inventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Patent number: 6303958Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a first hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: GrantFiled: June 11, 1998Date of Patent: October 16, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Patent number: 6190957Abstract: A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.Type: GrantFiled: June 2, 1999Date of Patent: February 20, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Mochizuki, Kumi Okuwada, Hiroyuki Kanaya, Osamu Hidaka, Susumu Shuto, Iwao Kunishima
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Patent number: 6045208Abstract: An ink-jet recording apparatus records an image onto a recording medium by flying an ink-droplet from an ink surface by a pressure of an ultrasonic beam. The apparatus including an ultrasonic generating element array having a plurality of ultrasonic elements arranged in an array for emitting ultrasonic beams, a driving device for applying a plurality of pulses having different phases from each other, and a converging device for converging the ultrasonic beams by interfering the ultrasonic beams with each other. The generating elements are simultaneously driven and sequentially shifted in an array direction, and the converging device converging the ultrasonic beams in a direction perpendicular to the array direction.Type: GrantFiled: July 11, 1995Date of Patent: April 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Shuzo Hirahara, Tutomu Saito, Hitoshi Nagato, Tetsuro Itakura, Satoshi Takayama, Hideki Nukada, Shunsuke Hattori, Noriko Y. Kudo, Shiroh Saitoh, Masami Sugiuchi, Yoichi Tokai, Fumihiko Murakami, Hisako Tanaka, Chiaki Tanuma, Mamoru Izumi, Isao Amemiya, Atsuko Nakamura, Seizaburou Shimizu, Kumi Okuwada
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Patent number: 5990507Abstract: A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.Type: GrantFiled: July 8, 1997Date of Patent: November 23, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Mochizuki, Kumi Okuwada, Hiroyuki Kanaya, Osamu Hidaka, Susumu Shuto, Iwao Kunishima
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Patent number: 5929473Abstract: An SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 nm) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.Type: GrantFiled: April 15, 1997Date of Patent: July 27, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Nishihori, Yoshiaki Kitaura, Yoshikazu Tanabe, Tomonori Aoyama, Kyoichi Suguro, Kumi Okuwada, Shuichi Komatsu, Kazuhide Abe
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Patent number: 5670808Abstract: A semiconductor device in which an SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 um) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.Type: GrantFiled: January 25, 1996Date of Patent: September 23, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Nishihori, Yoshiaki Kitaura, Yoshikazu Tanabe, Tomonori Aoyama, Kyoichi Suguro, Kumi Okuwada, Shuichi Komatsu, Kazuhide Abe
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Patent number: 5164882Abstract: A ceramic capacitor includes at least two opposing electrodes, and a dielectric ceramic composition arranged between the electrodes, wherein the ceramic composition is represented by a formula (Pb.sub.1-x Ae.sub.x) (Zr.sub.1-y Ti.sub.y)O.sub.3 (wherein x represents 0.15 to 0.90, y represents 0 to 0.80, and Ae represents at least one type of an element selected from the group consisting of Ca and Sr), and has a composition in which assuming that the total number of moles of elements constituting a site A consisting of Pb and Ae is (A) and that the total number of moles of elements constituting a site B consisting of Zr and Ti is (B), (A)/(B) is 1.00 or less. The site A of the dielectric ceramic composition may be partially substituted with Ba. The dielectric ceramic composition may be obtained by adding Nb, Cu, Bi, Mn, Co, Ag, Si, Ta, Mg, Zn, W and/or Ni to a composition which is represented by a formula (Pb.sub.1-x Ae.sub.x) (Zr.sub.1-y Ti.sub.y)O.sub.3 (wherein x represents 0.15 to 0.90, y represents 0 to 0.Type: GrantFiled: December 17, 1991Date of Patent: November 17, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Kanai, Yohachi Yamashita, Osamu Furukawa, Kumi Okuwada