Abstract: A delivery server includes a processor including hardware, the processor being configured to: transmit arrival information of a product to a user terminal carried by a user who has ordered the product; transmit, in a case where unattended delivery is instructed by the user terminal, unattended delivery information to a home delivery terminal of a delivery person who delivers the product, and request a signature of the user; transmit the signature information to the home delivery terminal in response to receiving signature information regarding the signature of the user from the user terminal; and transmit delivery completion information of the product to the user terminal.

Abstract: A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.

Abstract: In a separating device that separates a processor configured to perform process by using data recorded in a cache memory connected to the processor, a stopping unit, upon receiving a processor separation request, stops the processor from performing a new process; and a separation executing unit, upon completion of process being performed by the processor, separates the processor after invalidating the data recorded in the cache memory.

Abstract: A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.

Abstract: In a separating device that separates a processor configured to perform process by using data recorded in a cache memory connected to the processor, a stopping unit, upon receiving a processor separation request, stops the processor from performing a new process; and a separation executing unit, upon completion of process being performed by the processor, separates the processor after invalidating the data recorded in the cache memory.

Abstract: A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on information stored in the storage unit.

Abstract: A cache memory device comprises a secondary tag RAM that partially constitutes a secondary cache memory and employs a set associative scheme having a plurality of ways, and a secondary cache access controller that, when the number of ways in the secondary tag RAM is changed, allocates tags to respective entries so that the total number of entries constituting the secondary tag RAM and the total number of entries after the number of ways is changed are constant.

Abstract: A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on information stored in the storage unit.

Abstract: A cache memory device comprises a secondary tag RAM that partially constitutes a secondary cache memory and employs a set associative scheme having a plurality of ways, and a secondary cache access controller that, when the number of ways in the secondary tag RAM is changed, allocates tags to respective entries so that the total number of entries constituting the secondary tag RAM and the total number of entries after the number of ways is changed are constant.