Abstract: An image processing device for removing a noise having directionality in a first direction from an image containing the noise without affecting information on minute shading of luminance of the image, including: a high-pass filter unit configured to perform filtering processing on an image containing a noise having directionality in a horizontal direction with a high-pass filter in the horizontal direction; a low-pass filter unit configured to perform filtering processing on the image in a vertical direction with a low-pass filter; and an addition unit configured to add an image processed by the high-pass filter unit and an image processed by the low-pass filter unit.

Abstract: An electric connection inspection device includes: a cooling plate; an insulating plate provided on the cooling plate; a first measurement electrode provided on the insulating plate; and a second measurement electrode and a third measurement electrode provided above the first measurement electrode and located apart from the first measurement electrode. The insulating plate includes a variable thermal resistance mechanism. A semiconductor device can be installed between the first measurement electrode and the second measurement electrode and between the first measurement electrode and the third measurement electrode.

Abstract: In a silicon carbide substrate including: a SiC substrate; and a first semiconductor layer, a second semiconductor layer and a drift layer that are epitaxial layers sequentially formed on the SiC substrate, an impurity concentration of the first semiconductor layer is lower than impurity concentrations of the SiC substrate and the second semiconductor layer, and the second semiconductor layer is formed to have a high impurity concentration or a large thickness.

Abstract: To provide a technique capable of improving performance and reliability of a semiconductor device. An n?-type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p+-type body region (14), n+-type current spreading regions (16, 17), and a trench. TR are formed in the n?-type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p+-type body region (14), a side surface S1 of the trench TR is in contact with the n+-type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n+-type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the n?-type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface 32 of the trench.

Abstract: In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.

Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.

Abstract: In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.

Abstract: Provided is a silicon carbide semiconductor device in which SiC-MOSFETs are formed within an active region of an n-type silicon carbide semiconductor substrate, and a p+-type semiconductor region is formed on an upper surface of an epitaxial layer so as to surround the active region.

Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.

Abstract: Provided is a silicon carbide semiconductor device in which SiC-MOSFETs are formed within an active region of an n-type silicon carbide semiconductor substrate, and a p+-type semiconductor region is formed on an upper surface of an epitaxial layer so as to surround the active region.

Abstract: A Schottky junction type semiconductor device in which the opening width of a trench can be decreased without deteriorating the withstanding voltage. The cross sectional shape of a trench has a shape of a sub-trench in which the central portion is higher and the periphery is lower at the bottom of the trench, and a p type impurity is introduced vertically to the surface of the drift layer thereby forming a p+ SiC region, which is formed in contact to the inner wall of the trench having the sub-trench disposed therein, such that the junction position is formed more deeply in the periphery of the bottom of the trench than the junction position in the central portion of the bottom of the trench.

Abstract: In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment. A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.

Abstract: In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment. A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.