Patents by Inventor Kun LAN
Kun LAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240141480Abstract: Provided is a dual deposition chamber apparatus for producing silicon material, the apparatus including a furnace, a cooling jacket, a deposition device, and a vacuum extraction device. The cooling jacket communicates with the furnace, defines a space above the furnace, and includes an opening communicating with the space. The deposition device includes at least one first deposition substrate and at least one second deposition substrate. The at least one first deposition substrate and the at least one second deposition substrate are arranged side by side in the space, and respectively include a first inner wall surface and a second inner wall surface inclined downwards relative to a vertical axis. An uneven area is formed on the first inner wall surface and the second inner wall surface. The vacuum extraction device communicates with the opening of the cooling jacket.Type: ApplicationFiled: November 2, 2022Publication date: May 2, 2024Inventors: Chung-Wen LAN, Wen-Yi CHIU, Chao-Kun HSIEH, Chao-Hsiang HSIEH
-
Patent number: 11961803Abstract: The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.Type: GrantFiled: July 28, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Joung-Wei Liou, Chin Kun Lan
-
Publication number: 20240122077Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to form a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.Type: ApplicationFiled: November 13, 2023Publication date: April 11, 2024Inventors: Joung-Wei Liou, Chin Kun Lan
-
Publication number: 20240105136Abstract: An electronic device includes a display unit, a voltage generation unit, a grayscale adjustment unit, and an overdriving unit. The display unit has a relationship curve between the transmittance and the driving voltage. The relationship curve has a predetermined voltage value corresponding to the maximum transmittance. The voltage generation unit generates a first voltage according to a first grayscale, and generates a second voltage according to a second grayscale. The grayscale adjustment unit receives a first display grayscale value, and outputs the second grayscale value when the first display grayscale value is equal to the first grayscale. The overdriving unit overdrives the second voltage corresponding to the second grayscale to obtain a first target driving voltage, and it provides the first target driving voltage to the display unit.Type: ApplicationFiled: August 17, 2023Publication date: March 28, 2024Inventors: Syue-Ling FU, Yeh-Yi LAN, Cheng-Cheng PAN, Meng-Kun TSAI
-
Publication number: 20230413680Abstract: The present disclosure describes an exemplary method that forms spacer stacks with metallic compound layers. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.Type: ApplicationFiled: July 31, 2023Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Joung-Wei LIOU, Chin Kun LAN
-
Patent number: 11818964Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to from a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.Type: GrantFiled: March 16, 2022Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Joung-Wei Liou, Chin Kun Lan
-
Patent number: 11785858Abstract: An exemplary method that forms spacer stacks with metallic compound layers is disclosed. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.Type: GrantFiled: December 28, 2020Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Joung-Wei Liou, Chin Kun Lan
-
Patent number: 11769692Abstract: The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.Type: GrantFiled: June 5, 2019Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Joung-Wei Liou, Chin Kun Lan
-
Publication number: 20230008675Abstract: The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.Type: ApplicationFiled: July 28, 2022Publication date: January 12, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Joung-Wei Liou, Chin Kun Lan
-
Patent number: 11488825Abstract: A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH3 bonds less than the first content of Si—CH3 bonds.Type: GrantFiled: August 17, 2020Date of Patent: November 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Joung-Wei Liou, Chin Kun Lan
-
Publication number: 20220209101Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to from a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.Type: ApplicationFiled: March 16, 2022Publication date: June 30, 2022Inventors: Joung-Wei Liou, Chin Kun Lan
-
Patent number: 11283005Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to form a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.Type: GrantFiled: March 26, 2020Date of Patent: March 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Joung-Wei Liou, Chin Kun Lan
-
Patent number: 11178773Abstract: A conductor trace structure reducing insertion loss of circuit board, the circuit board laminates an outer layer circuit board, an inner layer circuit board and a glass fiber resin films which arranged between each board; before laminated process, the conductor traces of the inner layers had formed by etching of imaging transfer process and conductor traces had been roughed process for making the glass fiber resin films having good adhesive performance during laminating; before etching of imaging transfer process that forms the conductor traces of the outer layers or solder resist coat process or coating polymer materials, the conductor traces have been roughed process to make insulating resin layer of the solder resist coat or polymer materials to has better associativity; wherein a smooth trench is formed by physical or chemical process constructed on the roughed conductor traces surface to guide electric ions transmitted on these smooth trench surface to enhance electric ions transmission rate, resulting iType: GrantFiled: October 30, 2020Date of Patent: November 16, 2021Inventor: Sheng-Kun Lan
-
Patent number: 11139200Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes depositing a hard mask. A multi-layer structure is deposited over the hard mark. The multi-layer structure includes a bottom layer, a first middle layer over the bottom layer, a second middle layer over the first middle layer, and a top layer over the second middle layer. The first middle layer comprises a SiCxHyOz material in which the SiCxHyOz material has a silicon-to-silicon bond content in a range from about 0.5% to about 5%. The multi-layer structure is patterned to form a patterned first middle layer having openings. The hard mask is etched through the openings in the patterned first middle layer.Type: GrantFiled: December 5, 2019Date of Patent: October 5, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Joung-Wei Liou, Chin Kun Lan
-
Patent number: 11126247Abstract: A method for updating a power mode parameter combination, includes identifying a current hardware combination of a client host; loading and executing a current application program; loading a default profile according to the current application program to update a current power mode parameter combination of the current hardware combination; receiving a user-defined parameter combination to update the current power mode parameter combination of the current hardware combination; correlating the current application program, the current hardware combination and the updated current power mode parameter combination to generate a current profile as an updated default profile; and transmitting the current profile to a server as a candidate profile.Type: GrantFiled: September 4, 2019Date of Patent: September 21, 2021Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.Inventors: Ching-Hung Chao, Hou-Yuan Lin, Mou-Ming Ma, Chun-Kun Lan, Po-Chang Tseng, Hung-Yen Chen, Chun-Yu Wang, Yih-Neng Lin
-
Publication number: 20210136919Abstract: A conductor trace structure reducing insertion loss of circuit board, the circuit board laminates an outer layer circuit board, an inner layer circuit board and a glass fiber resin films which arranged between each board; before laminated process, the conductor traces of the inner layers had formed by etching of imaging transfer process and conductor traces had been roughed process for making the glass fiber resin films having good adhesive performance during laminating; before etching of imaging transfer process that forms the conductor traces of the outer layers or solder resist coat process or coating polymer materials, the conductor traces have been roughed process to make insulating resin layer of the solder resist coat or polymer materials to has better associativity; wherein a smooth trench is formed by physical or chemical process constructed on the roughed conductor traces surface to guide electric ions transmitted on these smooth trench surface to enhance electric ions transmission rate, resulting iType: ApplicationFiled: October 30, 2020Publication date: May 6, 2021Inventor: SHENG-KUN LAN
-
Publication number: 20210119116Abstract: The present disclosure describes an exemplary method that forms spacer stacks with metallic compound layers. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.Type: ApplicationFiled: December 28, 2020Publication date: April 22, 2021Inventors: Joung-Wei LIOU, Chin Kun LAN
-
Publication number: 20210098685Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to form a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.Type: ApplicationFiled: March 26, 2020Publication date: April 1, 2021Inventors: Joung-Wei Liou, Chin Kun Lan
-
Patent number: 10879456Abstract: An exemplary method for forming spacer stacks with metallic compound layers is provided. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.Type: GrantFiled: September 12, 2018Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Joung-Wei Liou, Chin Kun Lan
-
Publication number: 20200381252Abstract: A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH3 bonds less than the first content of Si—CH3 bonds.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Joung-Wei Liou, Chin Kun Lan