Abstract: A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal. A clock gating device is coupled to the control signal generating device, and receives the shift enable signal, the capture enable signal and the strobe signal. When the shift enable signal is enabled, the clock gating device controls the test clock signal as a serialized scan clock signal. When the strobe signal or the capture enable signal is enabled, the clock gating device controls the test clock signal as a scan clock signal.

Abstract: A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal. A clock gating device is coupled to the control signal generating device, and receives the shift enable signal, the capture enable signal and the strobe signal. When the shift enable signal is enabled, the clock gating device controls the test clock signal as a serialized scan clock signal. When the strobe signal or the capture enable signal is enabled, the clock gating device controls the test clock signal as a scan clock signal.

Abstract: A repairable multi-layer memory chip stack wherein each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.

Abstract: A test device for an SoC test architecture has a test input port, a test output port, a plurality of cores, a register, and a plurality of user defined logics. The register has a plurality of bits corresponding to the cores. Each of the user defined logics is connected to a corresponding bit of the register and a corresponding one of the cores. Each of the user defined logic receives a plurality of test control signals, and receives the corresponding bit of the register to change values of the test control signals. Outputs of each of the user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated.

Abstract: A repairable multi-layer memory chip stack is provided. Each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.

Abstract: A test device for an SoC test architecture has a test input port, a test output port, a plurality of cores, a register, and a plurality of user defined logics. The register has a plurality of bits corresponding to the cores. Each of the user defined logics is connected to a corresponding bit of the register and a corresponding one of the cores. Each of the user defined logic receives a plurality of test control signals, and receives the corresponding bit of the register to change values of the test control signals. Outputs of each of the user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated.

Abstract: A test device for a hierarchical test architecture is disclosed. The architecture includes cores for plural test layers, a top-level data register, and a top-level test controller. Cores for each test layer are hierarchical test circuits. The top-level test controller retrieves plural control signals, controls the top-level data register based on first type control signals in the control signals, and controls each core based on second type control signals in the control signals.

Abstract: A test device for the SoC test architecture is disclosed. The device comprises plural test groups connected in parallel and a test control flag register within a controller. Each test group comprises single or plural core circuits. The test control flag register enables a set of test signals to input in one of the test groups, testing the core circuits in the test group.

Abstract: Disclosed is a build-in self-diagnosis and repair method and apparatus in a memory with syndrome identification. It applies a fail-pattern identification and a syndrome-format structure to identify at least one type of faulty syndrome in the memory during a memory testing, then generates and exports fault syndrome information associated with the corresponding faulty syndrome. According to the fault syndrome information, the method applies a redundancy analysis algorithm, allocates spare memory elements and repairs the faulty cells in the memory. The syndrome-format structure respectively applies single-faulty-word-syndrome format, faulty-row-segment-syndrome format, and faulty-column-segment-syndrome format for different faulty syndromes, such as faulty row segments and single faulty words, faulty column segments and single faulty words, all of single faulty words, faulty row segments and faulty column segments, and so on.

Abstract: A test device for a hierarchical test architecture is disclosed. The architecture includes cores for plural test layers, a top-level data register, and a top-level test controller. Cores for each test layer are hierarchical test circuits. The top-level test controller retrieves plural control signals, controls the top-level data register based on first type control signals in the control signals, and controls each core based on second type control signals in the control signals.

Abstract: A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a decoding logic and a plurality of wrapper boundary registers. The decoding logic has a signal decoding table which receives and decodes the control signals and then issues decoded signals according to the signal decoding table. The WBR shifts, updates and captures the test signals for the core circuit to execute and output the result signals according to the decoded signals. In comparison with prior art, the testing time is reduced.

Abstract: Disclosed is a scan test data compression method and decoding apparatus for multiple-scan-chain designs. The apparatus comprises a on-chip decoder connected to a tester. The decoder includes a decoding buffer configured as a multilayer architecture, a controller, and a switching box for receiving a shift signal or a copy signal. The decoding buffer is used to store decoded test data. While the decoder decodes the encoded data, it transmits control signals to both the decoding buffer and the switching box from the controller, and sends the decoded data to scan chains of a CUT for testing through the decoding buffer. This invention has the advantages of simple encoding method, high compression rate, low power consumption in testing, and without the fault coverage loss.

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract: Disclosed is a build-in self-diagnosis and repair method and apparatus in a memory with syndrome identification. It applies a fail-pattern identification and a syndrome-format structure to identify at least one type of faulty syndrome in the memory during a memory testing, then generates and exports fault syndrome information associated with the corresponding faulty syndrome. According to the fault syndrome information, the method applies a redundancy analysis algorithm, allocates spare memory elements and repairs the faulty cells in the memory. The syndrome-format structure respectively applies single-faulty-word-syndrome format, faulty-row-segment-syndrome format, and faulty-column-segment-syndrome format for different faulty syndromes, such as faulty row segments and single faulty words, faulty column segments and single faulty words, all of single faulty words, faulty row segments and faulty column segments, and so on.

Abstract: A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a decoding logic and a plurality of wrapper boundary registers. The decoding logic has a signal decoding table which receives and decodes the control signals and then issues decoded signals according to the signal decoding table. The WBR shifts, updates and captures the test signals for the core circuit to execute and output the result signals according to the decoded signals. In comparison with prior art, the testing time is reduced.

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract: The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.

Abstract: A wrapper testing circuit and method thereof for System-On-a-Chip is provided for electrical tests of core circuits of an integrated circuit. The testing circuit includes a decoding logic with an encoding table for receiving test signals and delivering control signals in response to the test signals according to the table; a plurality of registers for saving the control signals temporarily and delivering the control signals to the core circuits; a bypass circuit for delivering the test signals; and an instruction register for saving the test signals temporarily and refreshing the data in the registers and the bypass circuits after the decoding logic issues the control signals. The encoding of the control signals is completed in one period. Compared with the serial encoding in the prior art, test time is reduced.

Abstract: The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.

Abstract: A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.