Abstract: An apparatus for detecting frequency of an input signal by counting the pulses of a reference signal of a predetermined frequency within one cycle of the input signal is disclosed. The apparatus includes a first and a second latch for latching the number of pulses of the reference signal for two consecutive periods of the input signal. In response to the reference signal, a comparator is used to compare the output value of the first and the second latch. When they are different, a flip-flop generates an interrupt signal to a microprocessor. The microprocessor reads the updated number of pulses and generates an updated frequency value based on the updated number of pulses and the predetermined frequency of the reference signal.

Abstract: A apparatus for generating an output signal of a desired pulse width is disclosed. The apparatus comprises a flip-flop, a delay circuit and a clear circuit. The flip-flop, in response to a first trigger signal, outputs the output signal at an output terminal. The delay circuit generates a second trigger signal by delaying the output signal for a predetermined amount of time. The clear circuit, in response to the second trigger signal, generates a clear signal to said flip-flop in order to clear the output signal. The desired pulse width of the output signal is controlled by the predetermined amount of time set in the delay circuit.

Abstract: The apparatus of the invention includes an edge detection circuit, a divide-by-N circuit and a latch. The edge detection circuit, responsive to an edge of the input signal, generates a trigger signal of a first frequency. The divide-by-N circuit inputs the trigger signal and generates a latch signal of a second frequency. The second frequency is equal to the first frequency divided by N. The latch inputs the input signal, and responsive to the latch signal, latches the input signal and outputs a polarity value representative of the polarity of the input signal.