Abstract: A thin film transistor device structure and a method for fabricating the thin film transistor device structure each comprise a thin film transistor device formed over a substrate. The thin film transistor device structure also comprises a passivation layer formed of a silicon rich silicon oxide material formed over the thin film transistor device. The passivation layer formed of the silicon rich silicon oxide material provides the thin film transistor device with enhanced performance.

Abstract: Provided is an integrated circuit (IC) having a strengthened passivation layer. In one example, the IC comprises a semiconductor substrate, a multilevel interconnect structure formed on the semiconductor substrate, and a multilayer passivation structure overlying the multilevel interconnect structure. At least one metal line of the multilevel interconnect structure forms a taper profile.

Abstract: A surface-mount-enhanced lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein a dam bar structure between any two neighboring lead frames of a lead frame module plate is formed with an indentation and at least a solder metal layer is applied on the bottom surface of the lead frame and the indentation. A singulation process is performed along the indentation to separate the lead frame module plate mounted with semiconductor chips and package body into a plurality of packages. Therefore, the indentation and the solder metal layer applied thereon can provide solder paste improved wettability and increased solder surface, while the semiconductor package with the lead frame is mounted on an external device via a surface-mount-technology, so as to prevent problems of signal transmission owing to separation of solder joint from solder open.

Abstract: A method and a system of wire bonding for use in semiconductor package fabrication are proposed. When one wire-bonded substrate unit of a substrate mounted with chips is introduced into a testing region, a next adjacent substrate unit is simultaneously formed with bonding wires in a wire-bonding region. In the testing region, the wire-bonded substrate unit is tested for wire bonding quality. If no wire opening or short occurs, the wire-bonded substrate unit is readily used for subsequent package fabrication. If wire opening or short is detected, a controlling module associated with the testing region generates a control signal to the wire-bonding region for interrupting a wire-bonding process, whereby causes of wire opening or short are overcome, and defective bonding wires are reworked. Therefore, inferiors or malfunction is timely detected, making overall fabrication process more time-effectively implemented; and inferiors are reworked for later usage, thereby significantly reducing fabrication costs.

Abstract: A new method is provided for the creation of an aluminum bump on a surface of a semiconductor device. A patterned layer of aluminum overlying a substrate is created, the patterned layer of aluminum is the layer of aluminum over which a contact bump is to be created. A layer of passivation is deposited, a first layer of photoresist is deposited for the creation of an opening in the layer of passivation that partially exposed the surface of the patterned layer of aluminum. This patterned first layer of photoresist remains in place, a layer of aluminum is sputter deposited, a second layer of photoresist is deposited which is patterned and etched for the creation of the aluminum bump overlying the patterned layer of aluminum. The aluminum solder bump is created by etching the deposited layer of aluminum. After the solder bump has been created, the patterned first and the second layers of photoresist are removed in one processing step, leaving in place the solder bump.

Abstract: A multi-die IC package structure and a method of manufacturing this multi-die IC package structure are proposed. This multi-die IC package structure is constructed on a lead frame including an inner-lead part having a plurality of inner leads surrounding a cavity in the center thereof, without the forming of a die pad. Next, a stacked multi-die structure is mounted on the inner-lead part of the lead frame, which is formed in such a manner the undermost semiconductor die has its non-circuit surface insulatively attached to the inner-lead part of the lead frame and its circuit surface insulatively attached to the overlying one, and also in such a manner that each of the semiconductor dies other than the undermost one has its non-circuit surface insulatively attached to the circuit surface of the underlying one. By the proposed method, the overall packaging process is significantly less complex than the prior art, thus allowing the manufacture process more cost-effective to carry out.

Abstract: A QFN package comprising a die pad, which has a first upper surface and a corresponding first lower surface, and at least a loop shaped groove conformal to, and inside the periphery of, the first lower surface of the die pad. A plurality of leads are formed and located along the boundary edges of the die pad. Each lead has a second upper surface and a corresponding second lower surface. A chip has an active surface and a corresponding back surface, and its back surface is adhered on the first upper surface of the die pad. A plurality of bonding pads is formed on the active surface of the chip, and are electrically connected to the leads. A molding compound, which encapsulates the chip, the die pad and the leads, leaves exposed on the first lower surface of the die pad and the second lower surfaces of the leads.

Abstract: A disturbing plate structure having at least one down set, applicable in a lead frame-type package in a semiconductor. The disturbing plate has at least a lead frame, a die, a glue layer, a plurality of disturbing plates, a top mold compound, and a bottom mold compound. The lead frame has a plurality of leads. Two disturbing plates are located on two sides of the die. A space is formed by bending a first bent portion and a second bent portion of the disturbing plate down. Finally, the lead frame is encapsulated with a mold compound. By adjusting the size of the space formed by the first bent portion and the second bent portion, the top mold compound section has substantially the same volume as the bottom mold compound section to finish the packaging and forming.

Abstract: A method is proposed for forming a constricted-mouth dimple structure on a lead-frame die pad for an integrated circuit (IC) package. This method can help secure the molded compound of the integrated circuit package more firmly in position to the die pad so that the molded compound would be less likely subjected to delamination. This method is charaterized in the use of a stamping process to punch on a selected part of the die pad that is located around the mouth of an originally-formed inwardly-tapered dimple structure, thereby narrowing the mouth of the inwardly-tapered dimple structure, resulting in the forming of the intended constricted-mouth dimple structure. Since this method requires only an additional stamping process to narrow the originally-formed inwardly-tapered dimple structure, it is much easier and more cost-effective to implement than the prior art.