Abstract: The subject application relates to a server, terminal and non-transitory computer-readable medium. The server for handling streaming data for a live streaming, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: recording the streaming data for the live streaming; storing the streaming data as archive contents with first identifier; receiving interaction information during the live streaming; storing the interaction information as contexts with second identifier, transmitting the archive contents with first identifier to a first user terminal; and transmitting the contexts to the first user terminal according to the first identifier and the second identifier. According to the subject application, the archive contents may be more immersive and the user experience may be enhanced.

Abstract: A driver circuit has a pad that may be utilized for programming a core circuit or receiving a data signal. A trace high circuit receives a pad voltage signal from the pad, and outputs a trace high voltage approximating a higher voltage of the pad voltage signal and the power supply voltage. A level shifter and a first inverter output a pull high control signal generated by inverting and level shifting a programming control signal. An ESD blocking circuit selectively blocks the pad voltage signal from reaching the core circuit depending on the pad voltage signal and the level-shifted programming control signal. A pull high circuit receives the pull high control signal and the power supply voltage, and outputs the power supply voltage to the core circuit when the pull high control signal is lower than the power supply voltage.

Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between a first terminal and a second terminal of an integrated circuit. The integrated circuit receives an input signal through the first terminal. The second terminal is coupled to a voltage source. The ESD protection circuit includes a PMOS transistor and a deep N-well NMOS transistor. When the static electricity is inputted to the first terminal, the static electricity flows to the voltage source through the corresponding parasitic diode and the corresponding parasitic bipolar transistor of the PMOS transistor and the deep N-well NMOS transistor. In addition, the input signal is not affected by the ESD protection circuit because the parasitic diodes of the PMOS transistor and the deep N-well NMOS transistor are reversely connected. Thus, the ESD protection circuit prevents the integrated circuit from being damaged by the static electricity and increases the operation voltage range of the input signal.

Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.

Abstract: An electrostatic discharge (ESD) protection circuit is electrically connected to a core circuit for preventing ESD charges from reaching the core circuit. The ESD protection circuit includes a pad, a pass transistor, a transistor, a capacitor, a resistor, and a delay trigger unit. The pass transistor controls passage of charges from the pad to the core circuit. The transistor sinks ESD charges during an ESD zapping event. The capacitor and the resistor couple voltage at the pad to a control electrode of the transistor for turning on the transistor during the ESD zapping event. The delay trigger unit retards transmission of low voltage to a control electrode of the pass transistor for keeping the pass transistor turned off during the ESD zapping event.

Abstract: A flash memory circuit with ESD protection includes a plurality of flash memory blocks, a pad, an ESD transistor, a pass transistor, and a gate driving circuit. The gate driving circuit has an inverter circuit for receiving a control voltage and outputting an output voltage, a resistor for receiving a pad voltage from the pad, and a capacitor for delaying a change in the control voltage. The ESD transistor is coupled to the pad, a power supply, and the output terminal of the inverter circuit. The pass transistor is coupled to one of the flash memory blocks and the pad, and is controlled by the output voltage. A well terminal of the pass transistor is coupled to the resistor for keeping the pass transistor turned off during electrostatic discharge through the pad.

Abstract: A driver circuit has a pad that may be utilized for programming a core circuit or receiving a data signal. A trace high circuit receives a pad voltage signal from the pad, and outputs a trace high voltage approximating a higher voltage of the pad voltage signal and the power supply voltage. A level shifter and a first inverter output a pull high control signal generated by inverting and level shifting a programming control signal. An ESD blocking circuit selectively blocks the pad voltage signal from reaching the core circuit depending on the pad voltage signal and the level-shifted programming control signal. A pull high circuit receives the pull high control signal and the power supply voltage, and outputs the power supply voltage to the core circuit when the pull high control signal is lower than the power supply voltage.

Abstract: A pad circuit includes a pad, a gate driving circuit, a voltage selection circuit, and an ESD detection/avoiding circuit. The gate driving circuit is used to discharge the ESD induced current. The ESD detection/avoiding circuit is used to isolate the ESD induced voltage. The voltage selection circuit selects a higher voltage from a power/ground terminal and the pad and outputs it to the gate driving circuit, so that the pad circuit can be used for the programming and 1/0 operations.