Abstract: The present invention relates to the technical field of composite materials, and in particular to a fiber composite material and a preparation method thereof. The preparation method comprises: A) uniformly dispersing nanoparticles in a solvent to obtain a nanoparticle dispersion; B) uniformly spray-coating the nanoparticle dispersion on a chopped fiber nonwoven fabric, and drying the fabric to obtain a nano-modified chopped fiber nonwoven fabric; C) intercalating the nano-modified chopped fiber nonwoven fabric between fiber preforms, and subjecting the obtained material and a resin matrix to composite molding by a molding process to obtain a fiber composite material. In the present invention, firstly nanoparticles are uniformly dispersed in a solvent to obtain a nanoparticle dispersion; secondly, the chopped fiber and the nanoparticles cooperate to construct a multi-scale interlaminar toughening phase, which significantly improves the interlaminar fracture toughness of the fiber composite material.

Abstract: A design method applied to a capacitor array is provided. The capacitor array includes multiple preset capacitor units, and each preset capacitor includes multiple unit capacitors. The method includes: acquiring unit simulation models of the preset capacitor units; acquiring a first simulation model of the capacitor array based on an arrangement manner of the preset capacitor units in the capacitor array and the unit simulation models of the preset capacitor unit; acquiring an arrangement direction of the preset capacitor units based on the arrangement manner, establishing a parasitic resistance equivalent test structure of a group of preset capacitor units in the same arrangement direction; obtaining a parasitic resistance of each preset capacitor unit based on the parasitic resistance equivalent test structure; and establishing a second simulation model representing the capacitor array based on the parasitic resistance of each preset capacitor unit and the first simulation model.

Abstract: Embodiments provide a dummy metal filling method and apparatus, a device and a medium, and relates to the field of semiconductor fabrication technologies. The method includes: providing an initial layout including a potential line; determining same-layer and same-net metal wires of each metal pattern layer based on a wiring connection relationship in the initial layout; determining a to-be-filled region in the each metal pattern layer based on the same-layer and same-net metal wires; filling same-layer metal wires into the to-be-filled region in the each metal pattern layer, and adding a connection hole, such that the same-layer metal wires are connected to the same potential line; and adding dummy metal on a layout where the filling the same-layer metal wires is completed, to output a target layout.

Abstract: The present disclosure provides a semiconductor structure, including: a plurality of metal layers and a substrate, wherein the plurality of metal layers include a first metal layer, a second metal layer, and a third metal layer; a plurality of virtual metal blocks and at least one signal line are disposed on the metal layers; the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate; a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate is greater than a first distance between the projection of the target signal line on the substrate and a projection of a first virtual metal block on the substrate; the target signal line is located on the first metal layer.

Abstract: A semiconductor structure includes a plurality of metal layers and a substrate. The plurality of metal layers are provided with a plurality of virtual metal blocks and at least one signal line. A first projection of a first virtual metal block on the substrate is a polygon, the first projection has a plurality of effective sides opposite to a second projection of a target signal line on the substrate, and differences from the plurality of effective sides of the first projection to a straight line where the second projection is located are different, and the first virtual metal block is a virtual metal block, closest to the target signal line, on the target metal layer, and the target metal layer is a metal layer where the target signal line is located.

Abstract: A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.

Abstract: A simulation method, apparatus, and a storage medium are provided. The simulation method includes: obtaining a pre-built local simulation model of a capacitor array region, wherein the local simulation model is configured to represent first simulation parameters of the capacitor array region; creating a local parameter netlist of a non-capacitor array region, wherein the local parameter netlist includes second simulation parameters of the non-capacitor array region; creating an overall parameter netlist of a peripheral region based on the local simulation model and the local parameter netlist, wherein the overall parameter netlist represents overall simulation parameters of the peripheral region, and the overall simulation parameters include the first simulation parameters and the second simulation parameters; and performing simulation on the peripheral region based on the overall parameter netlist.

Abstract: A design method applied to a capacitor array is provided. The capacitor array includes multiple preset capacitor units, and each preset capacitor includes multiple unit capacitors. The method includes: acquiring unit simulation models of the preset capacitor units; acquiring a first simulation model of the capacitor array based on an arrangement manner of the preset capacitor units in the capacitor array and the unit simulation models of the preset capacitor unit; acquiring an arrangement direction of the preset capacitor units based on the arrangement manner, establishing a parasitic resistance equivalent test structure of a group of preset capacitor units in the same arrangement direction; obtaining a parasitic resistance of each preset capacitor unit based on the parasitic resistance equivalent test structure; and establishing a second simulation model representing the capacitor array based on the parasitic resistance of each preset capacitor unit and the first simulation model.

Abstract: A lead frame array for carrying chips includes a plurality of lead frames. Any four lead frames adjacent to each other and have two pairs of linking bridge groups which are connected any two lead frames adjacent to each other by one of the linking bridge groups. Each linking bridge group has an inner linking bridge, a slanted linking bridge and an outer linking bridge. An LED package structure with multiple chips is further provided, which includes a lead frame formed by cutting the lead frame array.

Abstract: A single phase brushless high-speed motor, comprising: an outer housing, a stator assembly, and a rotor assembly; the stator assembly including a coil bobbin, stator coils and a stator core; the stator core including two core blocks, which comprise tooth portions, two opposite ends of the tooth portions being provided with a first magnetic yoke and a second magnetic yoke; the tooth portions of the stator core being engaged with each other to form an inner hole of the stator; the rotor assembly comprising an integral bearing, one end of the integral bearing being connected to an impeller, and the other end being mounted around magnets, which form magnetic body having two poles. The volume of the single-phase brushless motor is decreased and the requirements for the miniaturization of single-phase brushless motors are satisfied by arranging a mounting structure comprising a stator assembly and a rotor assembly.

Abstract: A single phase brushless high-speed motor, comprising: an outer housing, a stator assembly, and a rotor assembly; the stator assembly including a coil bobbin, stator coils and a stator core; the stator core including two core blocks, which comprise tooth portions, two opposite ends of the tooth portions being provided with a first magnetic yoke and a second magnetic yoke; the tooth portions of the stator core being engaged with each other to form an inner hole of the stator; the rotor assembly comprising an integral bearing, one end of the integral bearing being connected to an impeller, and the other end being mounted around magnets, which form magnetic body having two poles. The volume of the single-phase brushless motor is decreased and the requirements for the miniaturization of single-phase brushless motors are satisfied by arranging a mounting structure comprising a stator assembly and a rotor assembly.

Abstract: An LED package structure includes an LED frame, a driver frame unit, a housing, LED chips, a driver chip, and a light-permeable package body. The LED frame includes a carrying segment and two bent leads connected to the carrying segment. The driver frame unit includes two side frames each having a functional segment and a bent lead. The housing has a cavity exposing the carrying segment and the two functional segments. The bent leads protrude from a lateral surface of the housing, and curvedly extend to a bottom surface of the housing. The LED chips are mounted on the carrying segment. The driver chip is fixed to one of the two functional segments, and is electrically connected to the other functional segment and the LED chips. The light-permeable package body is filled in the cavity so as to embed the LED chips and the driver chip.

Abstract: A lead frame array for carrying chips includes a plurality of lead frames. Any four lead frames adjacent to each other and have two pairs of linking bridge groups which are connected any two lead frames adjacent to each other by one of the linking bridge groups. Each linking bridge group has an inner linking bridge, a slanted linking bridge and an outer linking bridge. An LED package structure with multiple chips is further provided, which includes a lead frame formed by cutting the lead frame array.

Abstract: An LED package structure includes an LED frame, a driver frame unit, a housing, LED chips, a driver chip, and a light-permeable package body. The LED frame includes a carrying segment and two bent leads connected to the carrying segment. The driver frame unit includes two side frames each having a functional segment and a bent lead. The housing has a cavity exposing the carrying segment and the two functional segments. The bent leads protrude from a lateral surface of the housing, and curvedly extend to a bottom surface of the housing. The LED chips are mounted on the carrying segment. The driver chip is fixed to one of the two functional segments, and is electrically connected to the other functional segment and the LED chips. The light-permeable package body is filled in the cavity so as to embed the LED chips and the driver chip.

Abstract: A wearable apparatus and a photoplethysmograph (PPG) sensor unit are provided. The wearable apparatus includes a wearable holder and a physiological information measurement module configured to the wearable holder. The physiological information measurement module includes a circuit board, an electrocardiograph (ECG) sensor unit and a PPG sensor unit. The PPG sensor unit is disposed on the circuit board and adapted to be used in conjunction with the ECG sensor unit electrically connected to a first pad and a second pad on the circuit board. The PPG sensor unit includes a grid having a plurality of accommodating spaces, a lighting element arranged in one of the accommodating spaces, and a photo sensor arranged in another accommodating space. The grid includes an inner conductive contact portion exposed from the wearable holder, facing an inner side of the wearable holder and electrically connected to the second pad.

Abstract: A light-emitting display has a circuit board, a spacer, a phosphor film, and a housing. The circuit board is provided with at least one light source. The spacer is disposed on a top surface of the circuit board. The spacer has a through hole which runs through the spacer from top to bottom and corresponds to the at least one light source and the phosphor film respectively. The housing has a reflecting portion and an accommodating space below the reflecting portion. The reflecting portion is located over the phosphor film. The accommodating space accommodates the circuit board, the spacer, and the phosphor film. The present disclosure also provides a method for forming the light-emitting display.

Abstract: The instant disclosure relates to a flip-chip LED package module and a method of manufacturing thereof. The method of manufacturing flip-chip LED package module comprises the following steps. A plurality of LEDs is disposed on a carrier. A packaging process is forming a plurality of transparent lens corresponding to LEDs and binding each other by a wing portion. A separating process is proceeding to form a plurality of flip-chip LED structures without the carrier. A bonding process is proceeding to attach at least one flip-chip LED structure on the circuit board.

Abstract: A light-emitting display has a circuit board, a spacer, a phosphor film, and a housing. The circuit board is provided with at least one light source. The spacer is disposed on a top surface of the circuit board. The spacer has a through hole which runs through the spacer from top to bottom and corresponds to the at least one light source and the phosphor film respectively. The housing has a reflecting portion and an accommodating space below the reflecting portion. The reflecting portion is located over the phosphor film. The accommodating space accommodates the circuit board, the spacer, and the phosphor film. The present disclosure also provides a method for forming the light-emitting display.

Abstract: A wearable apparatus and a photoplethysmograph (PPG) sensor unit are provided. The wearable apparatus includes a wearable holder and a physiological information measurement module configured to the wearable holder. The physiological information measurement module includes a circuit board, an electrocardiograph (ECG) sensor unit and a PPG sensor unit. The PPG sensor unit is disposed on the circuit board and adapted to be used in conjunction with the ECG sensor unit electrically connected to a first pad and a second pad on the circuit board. The PPG sensor unit includes a grid having a plurality of accommodating spaces, a lighting element arranged in one of the accommodating spaces, and a photo sensor arranged in another accommodating space. The grid includes an inner conductive contact portion exposed from the wearable holder, facing an inner side of the wearable holder and electrically connected to the second pad.

Abstract: The instant disclosure relates to a flip-chip LED package module and a method of manufacturing thereof. The method of manufacturing flip-chip LED package module comprises the following steps. A plurality of LEDs is disposed on a carrier. A packaging process is forming a plurality of transparent lens corresponding to LEDs and binding each other by a wing portion. A separating process is proceeding to form a plurality of flip-chip LED structures without the carrier. A bonding process is proceeding to attach at least one flip-chip LED structure on the circuit board.