Patents by Inventor Kung-Chen Yeh
Kung-Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990429Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.Type: GrantFiled: November 28, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Wei Wu, Ying-Ching Shih, Kung-Chen Yeh, Li-Chung Kuo, Pu Wang, Szu-Wei Lu
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Patent number: 11948896Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.Type: GrantFiled: July 26, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
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Publication number: 20230092361Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Inventors: Chih-Wei Wu, Ying-Ching Shih, Kung-Chen Yeh, Li-Chung Kuo, Pu Wang, Szu-Wei Lu
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Publication number: 20230032291Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.Type: ApplicationFiled: October 10, 2022Publication date: February 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kung-Chen Yeh, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih
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Patent number: 11515267Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.Type: GrantFiled: December 7, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Wei Wu, Li-Chung Kuo, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Kung-Chen Yeh
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Patent number: 11508692Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.Type: GrantFiled: June 1, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kung-Chen Yeh, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih
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Publication number: 20220359430Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu TSAI, Kung-Chen YEH, I-Ting HUANG, Shih-Ting LIN, Szu-Wei LU
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Publication number: 20220336412Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kung-Chen Yeh, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih
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Patent number: 11476205Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure. The first stacked die package structure includes a plurality of memory dies. The underfill layer is over the first stacked die package structure. The underfill layer includes a first protruding portion that extends below a top surface of the through substrate via structure. The package layer is over the underfill layer. The package layer has a second protruding portion that extends below the top surface of the through substrate via structure.Type: GrantFiled: February 9, 2021Date of Patent: October 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
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Patent number: 11164824Abstract: A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.Type: GrantFiled: May 4, 2020Date of Patent: November 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, Li-Chung Kuo, Szu-Wei Lu, Ying-Ching Shih
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Publication number: 20210202436Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.Type: ApplicationFiled: June 1, 2020Publication date: July 1, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kung-Chen Yeh, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih
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Publication number: 20210167024Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure. The first stacked die package structure includes a plurality of memory dies. The underfill layer is over the first stacked die package structure. The underfill layer includes a first protruding portion that extends below a top surface of the through substrate via structure. The package layer is over the underfill layer. The package layer has a second protruding portion that extends below the top surface of the through substrate via structure.Type: ApplicationFiled: February 9, 2021Publication date: June 3, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu TSAI, Kung-Chen YEH, I-Ting HUANG, Shih-Ting LIN, Szu-Wei LU
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Publication number: 20210118817Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Inventors: Chih-Wei Wu, Li-Chung Kuo, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Kung-Chen Yeh
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Publication number: 20210066211Abstract: A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.Type: ApplicationFiled: May 4, 2020Publication date: March 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, Li-Chung Kuo, Szu-Wei Lu, Ying-Ching Shih
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Patent number: 10923438Abstract: A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.Type: GrantFiled: April 26, 2019Date of Patent: February 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
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Patent number: 10872871Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate.Type: GrantFiled: May 7, 2019Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Hui Huang, Kuan-Yu Huang, Shang-Yun Hou, Yushun Lin, Heh-Chang Huang, Shu-Chia Hsu, Pai-Yuan Li, Kung-Chen Yeh
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Patent number: 10861799Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.Type: GrantFiled: May 17, 2019Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Li-Chung Kuo, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Kung-Chen Yeh
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Publication number: 20200365525Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.Type: ApplicationFiled: May 17, 2019Publication date: November 19, 2020Inventors: Chih-Wei Wu, Li-Chung Kuo, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Kung-Chen Yeh
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Publication number: 20200343198Abstract: A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.Type: ApplicationFiled: April 26, 2019Publication date: October 29, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Fu TSAI, Kung-Chen YEH, I-Ting HUANG, Shih-Ting LIN, Szu-Wei LU
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Publication number: 20200203299Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate.Type: ApplicationFiled: May 7, 2019Publication date: June 25, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Hui HUANG, Kuan-Yu HUANG, Shang-Yun HOU, Yushun LIN, Heh-Chang HUANG, Shu-Chia HSU, Pai-Yuan LI, Kung-Chen YEH