Abstract: A switch detecting a slow drain situation and providing a slow drain primitive to the slow draining device, such as a storage unit. The slow draining device detects the slow drain primitive and provides a throttling message to the relevant sources of frames being received by the slow draining device. The use of a primitive instead of a frame allows the slow condition notification to be provided even when there is no available credit for sending a frame.

Abstract: Systems for performing inline wire speed data deduplication are described herein. Some embodiments include a device for inline data deduplication that includes one or more input ports for receiving an input data stream containing duplicates, one or more output ports for providing a data deduplicated output data stream, and an inline data deduplication engine coupled to said one or more input ports and said one or more output ports to process input data containing duplicates into output data which is data deduplicated, said inline data deduplication engine having an inline data deduplication bandwidth of at least 4 Gigabytes per second.

Abstract: A switch detecting a slow drain situation and providing a slow drain primitive to the slow draining device, such as a storage unit. The slow draining device detects the slow drain primitive and provides a throttling message to the relevant sources of frames being received by the slow draining device. The use of a primitive instead of a frame allows the slow condition notification to be provided even when there is no available credit for sending a frame.

Abstract: A switch according to the present invention can have a number of ports in an ASIC greater than the ASIC clock speed divided by the network protocol rate. The switch ASIC contains multiple blocks, each block having a number of ports equal to the ASIC clock speed divided the packet rate of the protocol. Each block has a number of queues equal to the total number of ports on the ASIC to receive packets. The queues are scheduled from each block into a number of outputs equal to the number of blocks. The outputs of each block are received by a scheduler which evaluates the packets available at the outputs of each block to determine the combination of outputs which provides the most connections that are ready for transmission. The combination with the most connections is then utilized to provide packets to the egress section of each block.

Abstract: Packets or data units and their related credit returns each include an assigned phase value. When a credit test is desired, the phase value of outgoing data units is changed, for example from 0 to 1, and a new counter is set to a value of the outstanding credits having the original phase value. With each original phase credit received, the counter value is decremented. When a credit having the new phase value is received, the counter value indicates the amount of any credit error and appropriate corrections may be made.

Abstract: Use of a hash operation based on selected information in the packet to select one of a set of enable vectors. The selected enable vector is then effectively ANDed with the link expansion vector to select the actual links to be used. The enable vectors vary by selecting a different link in the LAG port for each enable vector. Thus the hash is used to vary the link of the LAG port used to transmit the packet for that multicast packet.

Abstract: Systems for performing inline wire speed data deduplication are described herein. Some embodiments include a device for inline data deduplication that includes one or more input ports for receiving an input data stream containing duplicates, one or more output ports for providing a data deduplicated output data stream, and an inline data deduplication engine coupled to said one or more input ports and said one or more output ports to process input data containing duplicates into output data which is data deduplicated, said inline data deduplication engine having an inline data deduplication bandwidth of at least 4 Gigabytes per second.

Abstract: Systems for performing inline wire speed data deduplication are described herein. Some embodiments include a device for inline data deduplication that includes one or more input ports for receiving an input data stream containing duplicates, one or more output ports for providing a data deduplicated output data stream, and an inline data deduplication engine coupled to one or more input ports and one or more output ports to process input data containing duplicates into output data which is data deduplicated, where the inline data deduplication engine has an inline data deduplication bandwidth of at least 4 Gigabytes per second.

Abstract: Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links.

Abstract: A switch according to the present invention can have a number of ports in an ASIC greater than the ASIC clock speed divided by the network protocol rate. The switch ASIC contains multiple blocks, each block having a number of ports equal to the ASIC clock speed divided the packet rate of the protocol. Each block has a number of queues equal to the total number of ports on the ASIC to receive packets. The queues are scheduled from each block into a number of outputs equal to the number of blocks. The outputs of each block are received by a scheduler which evaluates the packets available at the outputs of each block to determine the combination of outputs which provides the most connections that are ready for transmission. The combination with the most connections is then utilized to provide packets to the egress section of each block.

Abstract: A switch creates and dynamically updates a latency map of a network to adjust routing of flows. Further, the network is monitored to detect latency issues and trigger a dynamic adjustment of routing based on the latency map. In this manner, a flow can be routed along a route (i.e., a faster route) that provides less latency than other available routes. The latency map can be generated based on latency probe packets that are issued from and returned to the source switch. By evaluating many such latent probe packets that have traveled along many available routes (e.g., corresponding to various ports of the switch), the switch or associated administrative logic can dynamically adjust the latency map to updated latency information of available routes. Therefore, responsive to a trigger, the source switch can dynamically adjust the routing of a flow based on latency issues discerned from the network.

Abstract: One embodiment of the present invention provides a system that facilitates automatic adjustment of logical channels in a Fiber Channel (FC) network. During operation, the system receives FC data frames. A respective data frame is associated with a logical channel. The bandwidth on an FC link can be allocated into a plurality of logical channels, and a respective logical channel is associated with a dedicated buffer and can transport a plurality of data flows with data frames of variable length. The system then identifies a slow data flow in a first logical channel. Next, the system assigns the slow data flow to a second logical channel, thereby preventing the slow data flow from slowing down other data flows in the first logical channel. The system subsequently forwards the data frames in the slow data flow on the second logical channel onto an outgoing link.

Abstract: Packets or data units and their related credit returns each include an assigned phase value. When a credit test is desired, the phase value of outgoing data units is changed, for example from 0 to 1, and a new counter is set to a value of the outstanding credits having the original phase value. With each original phase credit received, the counter value is decremented. When a credit having the new phase value is received, the counter value indicates the amount of any credit error and appropriate corrections may be made.

Abstract: Apparatuses and methods to mirror frames received at an input port or provided by an output port to a port not connected to the device performing the mirroring operation. A frame being sent to a diagnostic system has a mirror header added to allow the frame to be routed through any intervening switches in the same fabric. The final switch or the diagnostic system removes the mirror header. If the diagnostic system is attached in a different fabric, encapsulation and inter-fabric routing headers are added as needed to the frame containing the mirror header. This allows the frame to traverse multiple fabrics to reach the diagnostic system. The encapsulation and inter-fabric routing headers are removed as done normally. This allows a diagnostic system to be connected to any switch in the network, either in the same or a different fabric.

Abstract: A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.

Abstract: One embodiment of the present invention provides a system that facilitates automatic adjustment of logical channels in a Fibre Channel (FC) network. During operation, the system receives FC data frames. A respective data frame is associated with a logical channel. The bandwidth on an FC link can be allocated into a plurality of logical channels, and a respective logical channel is associated with a dedicated buffer and can transport a plurality of data flows with data frames of variable length. The system then identifies a slow data flow in a first logical channel. Next, the system assigns the slow data flow to a second logical channel, thereby preventing the slow data flow from slowing down other data flows in the first logical channel. The system subsequently forwards the data frames in the slow data flow on the second logical channel onto an outgoing link.

Abstract: One embodiment of the present invention provides a system that facilitates automatic adjustment of logical channels in a Fiber Channel (FC) network. During operation, the system receives FC data frames. A respective data frame is associated with a logical channel. The bandwidth on an FC link can be allocated into a plurality of logical channels, and a respective logical channel is associated with a dedicated buffer and can transport a plurality of data flows with data frames of variable length. The system then identifies a slow data flow in a first logical channel. Next, the system assigns the slow data flow to a second logical channel, thereby preventing the slow data flow from slowing down other data flows in the first logical channel. The system subsequently forwards the data frames in the slow data flow on the second logical channel onto an outgoing link.

Abstract: Systems for hardware-accelerated lossless data compression are described. At least some embodiments include data compression apparatus that includes a plurality of hash memories each associated with a different lane of a plurality of lanes (each lane including data bytes of a data unit being received by the compression apparatus), an array including array elements each including a plurality of validity bits (each validity bit within an array element corresponding to a different lane of the plurality of lanes), control logic that initiates a read of a hash memory entry if a corresponding validity bit indicates that said entry is valid, and an encoder that compresses at least the data bytes for the lane associated with the hash memory comprising the valid entry if said valid entry comprises data that matches the lane data bytes.

Abstract: A two-port memory having a read port, a write port and a plurality of identical single-port RAM banks. The capacity of one of the single-port RAM banks is used to resolve collisions between simultaneous read and write accesses to the same single-port RAM bank. A read mapping memory stores instance information that maps logical banks and a spare bank to the single-port RAM banks for read accesses. Similarly, a write mapping memory stores write instance information that maps logical banks and a spare bank to the single-port RAM banks for write accesses. If simultaneous read and write accesses are not mapped to the same single-port RAM bank, read and write are performed simultaneously. However, if a collision exists, the write access is re-mapped to a spare bank identified by the write instance information, allowing simultaneous read and write. Both read and write mapping memories are updated to reflect any re-mapping.

Abstract: A switch creates and dynamically updates a latency map of a network to adjust routing of flows. Further, the network is monitored to detect latency issues and trigger a dynamic adjustment of routing based on the latency map. In this manner, a flow can be routed along a route (i.e., a faster route) that provides less latency than other available routes. The latency map can be generated based on latency probe packets that are issued from and returned to the source switch. By evaluating many such latent probe packets that have traveled along many available routes (e.g., corresponding to various ports of the switch), the switch or associated administrative logic can dynamically adjust the latency map to updated latency information of available routes. Therefore, responsive to a trigger, the source switch can dynamically adjust the routing of a flow based on latency issues discerned from the network.