Patents by Inventor Kung-Yen Hsu

Kung-Yen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9042505
    Abstract: A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: May 26, 2015
    Assignee: MEDIATEK INC.
    Inventors: Chi-Feng Lin, Kung-Yen Hsu, Yu-Bang Nian
  • Publication number: 20150121120
    Abstract: A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Applicant: MEDIATEK INC.
    Inventors: Chi-Feng Lin, Kung-Yen Hsu, Yu-Bang Nian