Patents by Inventor Kunihiko Nakada
Kunihiko Nakada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200373575Abstract: A secondary battery includes: a solid electrolyte layer including at least one of water (H2O) and a hydroxyl group (—OH); a positive-electrode active material layer disposed on the solid electrolyte layer and including nickel hydroxide; a second electrode (positive electrode) disposed on the positive-electrode active material layer; a negative-electrode active material layer disposed on a lower surface of the solid electrolyte layer so as to be opposite to the positive-electrode active material layer, and including a titanium oxide compound (TiOx) including at least one of water and a hydroxyl group; a first electrode (negative electrode) disposed on a lower surface of the negative-electrode active material layer so as to be opposite to the second electrode; a p type semiconductor layer disposed between the positive-electrode active material layer and the second electrode; and an n type semiconductor layer disposed between the negative-electrode active material layer and the first electrode.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Inventors: Kazuyuki TSUNOKUNI, Takashi TONOKAWA, Kunihiko NAKADA, Yutaka KOSAKA
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Patent number: 7451485Abstract: A malfunction detection system is provided that can continue or terminate processing appropriately even if a malfunction occurs in an information processing unit. In this regard, the information processing unit receives branch direction information, carries out a conditional branch depending on the branch direction information, and performs an applicable operation on data I. At this time, the information processing unit performs an applicable operation on data J, other than the operated data I, in the conditional branch path and outputs the result for examination, thereby enabling validation of the conditional branch.Type: GrantFiled: April 18, 2002Date of Patent: November 11, 2008Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Watanabe, Takashi Endo, Masahiro Kaminaga, Kunihiko Nakada, Yuuichirou Nariyoshi, Chiaki Tanimoto
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Patent number: 7379967Abstract: The present invention relates to the improvement of the Bit Torrent protocol, which is one of the P2P protocols. A seeder flag is added to the active peer table. First a super seeder having the original is activated, and the super seeder is stopped when the total value of the seeder flags (number of activated seeders) reaches a certain level. The super seeders are activated only when the seeders having the original of a file are insufficient on the network, and are stopped when excessive. By this dynamic control, the number of activated processes of the super seeders can be decreased.Type: GrantFiled: January 28, 2005Date of Patent: May 27, 2008Assignee: Grid Solutions, Inc.Inventors: Masahiro Izutsu, Kunihiko Nakada, Michimasa Suzawa
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Patent number: 7201326Abstract: An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.Type: GrantFiled: December 29, 2003Date of Patent: April 10, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Endo, Masahiro Kaminaga, Takashi Watanabe, Kunihiko Nakada, Takashi Tsukamoto
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Publication number: 20070028133Abstract: The present invention relates to the improvement of the Bit Torrent protocol, which is one of the P2P protocols. A seeder flag is added to the active peer table. First a super seeder having the original is activated, and the super seeder is stopped when the total value of the seeder flags (number of activated seeders) reaches a certain level. The super seeders are activated only when the seeders having the original of a file are insufficient on the network, and are stopped when excessive. By this dynamic control, the number of activated processes of the super seeders can be decreased.Type: ApplicationFiled: January 28, 2005Publication date: February 1, 2007Applicant: ARGO-NOTES, INC.Inventors: Masahiro Izutsu, Kunihiko Nakada, Michimasa Suzawa
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Patent number: 7086087Abstract: It is a technological object of the present invention to provide an information processing device, a card and a card system that have a high level of security. In order to achieve the object described above, the present invention provides a data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line, the data processing apparatus having a means for changing power consumption on the signal line during transmission of a signal through the signal line in accordance with an actual state of the power consumption that would be observed when the means were not used.Type: GrantFiled: June 22, 2000Date of Patent: August 1, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masahiro Kaminaga, Takashi Endo, Masaru Ohki, Takashi Tsukamoto, Hiroshi Watase, Chiaki Terauchi, Kunihiko Nakada, Nobutaka Nagasaki, Satoshi Taira, Yuuichirou Nariyoshi, Yasuko Fukuzawa
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Patent number: 6907526Abstract: Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current. In a microcomputer having a module configuration including an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current.Type: GrantFiled: January 5, 2001Date of Patent: June 14, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Chiaki Tanimoto, Kunihiko Nakada, Takashi Tsukamoto, Shigeo Hirabayashi, Hiroshi Watase, Masatoshi Takahashi, Yuuichirou Nariyoshi
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Publication number: 20040136530Abstract: An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.Type: ApplicationFiled: December 29, 2003Publication date: July 15, 2004Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., LTD.Inventors: Takashi Endo, Masahiro Kaminaga, Takashi Watanabe, Kunihiko Nakada, Takashi Tsukamoto
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Patent number: 6691921Abstract: An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.Type: GrantFiled: August 14, 2002Date of Patent: February 17, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Endo, Masahiro Kaminaga, Takashi Watanabe, Kunihiko Nakada, Takashi Tsukamoto
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Publication number: 20030094499Abstract: An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.Type: ApplicationFiled: August 14, 2002Publication date: May 22, 2003Inventors: Takashi Endo, Masahiro Kaminaga, Takashi Watanabe, Kunihiko Nakada, Takashi Tsukamoto
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Publication number: 20020169969Abstract: A malfunction detection system that can continue or terminate processing appropriately even if a malfunction occurs in an information processing unit; wherein an information processing unit receives branch direction information, carries out a conditional branch depending on the branch direction information, and performs an applicable operation on data I; at this time, the information processing unit performs an applicable operation on data J other than the operated data I in the conditional branch path and outputs the result for examination, thereby enabling validation of the conditional branch.Type: ApplicationFiled: April 18, 2002Publication date: November 14, 2002Inventors: Takashi Watanabe, Takashi Endo, Masahiro Kaminaga, Kunihiko Nakada, Yuuichirou Nariyoshi, Chiaki Tanimoto
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Publication number: 20010047480Abstract: Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current. In a microcomputer having a module configuration including an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current.Type: ApplicationFiled: January 5, 2001Publication date: November 29, 2001Inventors: Chiaki Tanimoto, Kunihiko Nakada, Takashi Tsukamoto, Shigeo Hirabayashi, Hiroshi Watase, Masatoshi Takahashi, Yuuichirou Nariyoshi
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Publication number: 20010016910Abstract: Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current. In a microcomputer having a module configuration including an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current.Type: ApplicationFiled: January 5, 2001Publication date: August 23, 2001Inventors: Chiaki Tanimoto, Kunihiko Nakada, Takashi Tsukamoto, Shigeo Hirabayashi, Hiroshi Watase, Masatoshi Takahashi, Yuuichirou Nariyoshi
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Patent number: 5961578Abstract: In a microcomputer incorporating a microprocessor, the coprocessor having product-sum operation arithmetic units executes residue multiplications given by "A=A.multidot.B.multidot.R.sup.-1 mod N+kN", "A=A.sup.2 .multidot.R.sup.-1 mod N+kN" and "A=A.multidot.R.sup.-1 mod N 30 kN" and is provided with a multiplication function of executing a preprocessing "R.sup.2 mod N" at high speed. It is possible to perform a power-residue operation "X.sup.Y mod N" at high speed by the microprocessor, using these calculation functions of the coprocessor.Type: GrantFiled: June 26, 1997Date of Patent: October 5, 1999Assignee: Hitachi, Ltd.Inventor: Kunihiko Nakada
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Patent number: 5581698Abstract: An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provided which is capable of supplying selectively a signal, input to the internal bus, to a specified functional module in place of an individual signal.Type: GrantFiled: April 15, 1993Date of Patent: December 3, 1996Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Yoshiyuki Miwa, Tsuyoshi Jouno, Haruo Keida, Kunihiko Nakada, Hajime Yasuda
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Patent number: 5361374Abstract: A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two sorts of control procedures among HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a command of the processor.Type: GrantFiled: April 21, 1993Date of Patent: November 1, 1994Assignee: Hitachi, Ltd.Inventors: Hisao Sasaki, Takeshi Miyazaki, Shiro Baba, Kunihiko Nakada, Yasushi Akao
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Patent number: 5226173Abstract: A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a mode control data written in a mode control register by a processor.Type: GrantFiled: March 13, 1992Date of Patent: July 6, 1993Assignee: Hitachi, Ltd.Inventors: Hisao Sasaki, Takeshi Miyazaki, Shiro Baba, Kunihiko Nakada, Yasushi Akao
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Patent number: 5005121Abstract: A data processor controller for a microprogramming system is constructed with a single operation execution unit serving both a microprocessor and a peripheral device such as a direct memory access controller. In addition to the single operation execution unit, the controller includes a micro-memory which stores micro-instructions for controlling both the microprocessor and the peripheral device, and address registers, multiplexers and decoders integrated into a single device.Type: GrantFiled: March 20, 1989Date of Patent: April 2, 1991Assignee: Hitachi, Ltd.Inventors: Kunihiko Nakada, Yasushi Akao