Abstract: A driver circuit for driving a device or circuit disposed after it comprises a plurality of driving transistors connected in parallel, a selection unit for selecting one or more groups from a plurality of groups to each of which driving transistors having a power base of two with the same polarity belong and in which the number of driving transistors belonging to each group is different and a driving unit for driving driving transistors belonging to the group selected by the selection unit.

Abstract: A termination circuit for terminating a transmission line comprises a resistance unit which is formed by connecting a P-channel type MOS transistor and an N-channel type MOS transistor in parallel, and Thevenin termination is formed by providing this resistance unit between the transmission line and a power supply line and between the transmission line and a ground line.

Abstract: In an operation to supply an input signal IN having an amplitude equal to a first power-supply voltage VDD1 to the gate of a PMOS transistor PM51 operating at a second power-supply voltage VDD2 higher than the first power-supply voltage VDD1, the levels of signals are converted by using PMOS transistors PM1 to PM4. A signal obtained as a result of the conversion is output from the PMOS transistors PM1 and PM2, being used for controlling electrical conduction of a PMOS transistor PM51.

Abstract: An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Abstract: A driver circuit for driving a device or circuit disposed after it comprises a plurality of driving transistors connected in parallel, a selection unit for selecting one or more groups from a plurality of groups to each of which driving transistors having a power base of two with the same polarity belong and in which the number of driving transistors belonging to each group is different and a driving unit for driving driving transistors belonging to the group selected by the selection unit.

Abstract: A termination circuit for terminating a transmission line comprises a resistance unit which is formed by connecting a P-channel type MOS transistor and an N-channel type MOS transistor in parallel, and Thevenin termination is formed by providing this resistance unit between the transmission line and a power supply line and between the transmission line and a ground line.

Abstract: An interface circuit which is connected to a function unit such as a memory reduces the number of structural elements by using structural elements in common, and also realizes a plurality of different function circuits. The interface circuit connected with the function unit uses the structural elements for a plurality of circuits in common, and obtains necessary functions by controlling the structural elements. The interface circuit has first and second electronic devices such as FETs connected in series, and an external terminal, formed at an intermediate connected portion between the first electronic device and the second electronic device, to which the function unit is connected, and constitutes a function circuit part having different functions by controlling the first electronic device and the second electronic device.

Abstract: An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Abstract: An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Abstract: In an operation to supply an input signal IN having an amplitude equal to a first power-supply voltage VDD1 to the gate of a PMOS transistor PM51 operating at a second power-supply voltage VDD2 higher than the first power-supply voltage VDD1, the levels of signals are converted by using PMOS transistors PM1 to PM4. The sources of the PMOS transistors PM1 and PM3 are connected to a line of the first power-supply voltage VDD1 whereas the sources of the PMOS transistors PM2 and PM4 are connected to a line of the second power-supply voltage VDD2. The gate of the PMOS transistor PM4 is connected to the drains of the PMOS transistors PM1 and PM2. The gate of the PMOS transistor PM2 is connected to the drains of the PMOS transistors PM3 and PM4. An inverted signal of the input signal IN is supplied to the gate of the PMOS transistor PM1 and the input signal IN is supplied to the gate of the PMOS transistor PM2.

Abstract: An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Abstract: Method of data compression and restoration wherein an input data string including repetitive data more in number than the specified value is transformed into a data string having a format including the first region where non-compressed data are placed, the second region including a datum representative of a data string section which has undergone the compression process and information indicative of the number of repetitive data, i.e., the length of the data string section, and control information inserted at the front and back of the first region indicative of the number of data included in the first region, said transformed data string being recorded on the recording medium, and, for data reproduction, the first and second regions are identified on the basis of the control information read out on the recording medium so that the compressed data string section is transformed back to the original data string in the form of repetitive data.