Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.

Abstract: A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.

Abstract: A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.

Abstract: A method produces a semiconductor by conducting superimposed doping of a plurality of dopants in a semiconductor substrate, which includes evaporating a (2×n) structure by a first dopant and forming its thin line structure on the substrate, then bringing the semiconductor substrate to a temperature capable of epitaxial growth, vapor depositing a second or third or subsequent dopants above the semiconductor substrate where the first dopant has been deposited, then epitaxially growing a semiconductor crystal layer over the semiconductor substrate, subsequently forming a superimposed doping layer composed of the first, second, or the third or subsequent dopants in the semiconductor substrate, and applying an annealing treatment to the superimposed doping layer at a high temperature, thereby activating the plurality of dopants electrically or optically. Superimposed doping of a plurality kinds of elements as dopants is performed to a predetermined depth in the case of an elemental semiconductor.

Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.

Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing a nano-wire field effect transistor including two columnar members made of a silicon crystal configuring a nano-wire on a substrate are arranged on a substrate in parallel and one above the other, and an SOI substrate having a (100) surface orientation; processing a silicon crystal layer configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other as to face along the ridge lines of the triangular columnar members; and processing the triangular columnar member into a circular columnar member configuring a nano-wire by hydrogen-annealing or a thermal oxidation; and an integrated circuit including the transistor.

Abstract: A method for producing a semiconductor by conducting superimposed doping of a plurality of dopants in a semiconductor substrate, which includes evaporating a (2×n) structure by a first dopant and forming its thin line structure on the substrate, then bringing the semiconductor substrate to a temperature capable of epitaxial growth, vapor depositing a second or third or subsequent dopants above the semiconductor substrate where the first dopant has been deposited, then epitaxially growing a semiconductor crystal layer over the semiconductor substrate, subsequently forming a superimposed doping layer composed of the first, second, or the third or subsequent dopants in the semiconductor substrate, and applying an annealing treatment to the superimposed doping layer at a high temperature, thereby activating the plurality of dopants electrically or optically.

Abstract: A sound source management system for a telephone switching network is disclosed in which, in response to a sound source capturing request from a subscriber through a call processing unit, a sound source management unit drives an idle sound source detection unit to refer to a sound source management data storing unit, so as to detect an idle sound source connected to the own switching unit or connected to another switching units, and when an idle sound source is detected, the detected sound source is captured so that a sound from the captured sound source is sent to the subscriber, whereby a momentary resource shortage in each switching unit can be avoided economically and without affecting the traffic of the overall network.

Abstract: A dual gate structure field-effect transistor is manufactured by forming a trench in an SOI substrate comprised of a semiconductor support substrate, a buried insulation layer formed on the support substrate and an SOI semiconductor layer formed on the insulation layer, so as to extend from an upper surface of the SOI substrate through the SOI semiconductor layer and the buried insulation layer to the semiconductor support substrate, thereby dividing the SOI semiconductor layer into two SOI semiconductor layer regions that form a source electrode and a drain electrode; forming a gate electrode constituted of low resistance material in a portion of the trench in contact with the buried insulation layer, thereby self-aligning with the source electrode and drain electrode; forming a gate insulation layer on the gate electrode in contact with the buried insulation layer around the trench; forming a semiconductor conduction channel layer on the gate insulation layer in contact with the two SOI semiconductor layer

Abstract: A method for surface flattening a crystal substrate includes (a) processing a surface of a silicon single crystal substrate, the surface deviating by 0.1.degree. or less from the (001) plane, so as to form a processed zone thereon which is an obstacle to the movement of surface steps present on the surface of the silicon single crystal substrate and which is adjacent to a preselected region having a surface to be flattened when viewed on an atomic level; (b) holding the substrate processed in step (a) in a chamber having an adjustable degree of vacuum so that the substrate has a temperature which is controlled by direct-current passage and heating; and (c) heating the substrate to move the surface steps along the substrate from the preselected region and gather the surface steps in the processed zone, thereby forming a flat surface in the preselected region of the substrate when viewed on the atomic level.