Abstract: An ion sensor, an ion sensor manufacturing method, and a field asymmetric ion mobility spectrometry (FAIMS) system. The ion sensor includes an ion filter including a first electrode and a second electrode facing each other, an ion sensing electrode with which an ion that has passed through the ion filter collides, and an insulator to electrically insulate the ion sensing electrode from the first electrode and the second electrode. The method includes forming a first slit on an active layer of an at least one SOI substrate, the at least one SOI substrate including a base layer, an insulating layer on the base layer, and the active layer on the insulating layer, dividing the active layer into two, forming a second slit through the base layer, the second slit overlapping with the first slit in a planar view, and forming a third slit through the insulating layer.

Abstract: An analysis system includes: an ionizer to ionize sample gas so as to have a first polarity; a detection circuit to detect at least a part of ions of the sample gas; a housing accommodating the ionizer and the detection circuit; and a voltage generation circuit to apply a voltage having the first polarity to the housing to generate an electric field inside the housing between the ionizer and the detection circuit, the electric field having a first component in a first direction perpendicular to a second direction parallel to a flow direction of the sample gas and a second component in a third direction perpendicular to the first direction and the second direction.

Abstract: An ion sensor, an ion sensor manufacturing method, and a field asymmetric ion mobility spectrometry (FAIMS) system. The ion sensor includes an ion filter including a first electrode and a second electrode facing each other, an ion sensing electrode with which an ion that has passed through the ion filter collides, and an insulator to electrically insulate the ion sensing electrode from the first electrode and the second electrode. The method includes forming a first slit on an active layer of an at least one SOI substrate, the at least one SOI substrate including a base layer, an insulating layer on the base layer, and the active layer on the insulating layer, dividing the active layer into two, forming a second slit through the base layer, the second slit overlapping with the first slit in a planar view, and forming a third slit through the insulating layer.

Abstract: A sheet material identification device includes a humidity adjuster, a detector, and a controller. The humidity adjuster adjusts the humidity of a sheet material by causing the sheet material to either release or absorb moisture. The detector detects the humidity of the sheet material before and after the adjustment of the humidity. The controller calculates a first difference in humidity of the sheet material before and after the adjustment of the humidity, and identifies the type of sheet material on the basis of the first difference.

Abstract: A protection circuit module for a secondary battery including a wiring substrate including two battery-side external connection terminals provided on a top surface thereof, multiple load-side external connection terminals provided on a back surface opposite the top surface, and at least one cutout or through-hole in the wiring substrate; one or more electronic components provided on the wiring substrate; and two metal plates provided respectively on the two battery-side external connection terminals. The at least one cutout or through-hole is provided at a portion of the wiring substrate in which one of the two metal plates is provided, so that a part of the one of the two metal plates is exposed through the cutout or the through-hole when viewed from the back surface of the wiring substrate.

Abstract: To realize reduction in the size and cost of a protection circuit module for a secondary battery. A protection circuit module 1 for a secondary battery has at least a wiring board 2 having multiple battery-side external terminals 4a and multiple load-side external terminals 20a, and semiconductor components 12 and 14 mounted on the wiring board 2. On the wiring board 2, the battery-side external terminals 4a are disposed on a surface 2a, and the load-side external terminals 20a are disposed on a surface 2b on the opposite side. The semiconductor components 12 and 14 have multiple external connection terminals 12a and 14a arranged on a single plane surface, and are mounted face-down in a bare-chip state on the surface 2a of the wiring board 2.

Abstract: An electronic component device testing apparatus includes first contacts arrayed so that first ends of the first contacts positionally correspond to electrode pads arrayed on a surface of an electronic component device; base electrodes in contact with second ends of the first contacts; and one or more second contacts each being in contact with one of the first contacts at a position which is between the first end and the second end of the one of the first contacts and closer to the first end of the one of the first contacts.

Abstract: An RFID tag comprises a semiconductor chip storing therein information of an object to be discriminated and carrying out radio communication with a reader/writer device; and an antenna coil provided with a magnetic core member and connected electrically to the semiconductor chip. The semiconductor chip and the magnetic core member are wrapped by an insulation sheet carrying an interconnection pattern connecting a pad of the semiconductor chip and the antenna coil electrically and plural coil patterns on one side thereof. The plural coil patterns includes bar-shaped conductor patterns formed obliquely to the magnetic core member, each of the bar-shaped conductor patterns having an end connected to an end of an adjacent coil pattern, the bar-shaped conductor patterns thereby forming together a spiral coil around the magnetic core member. The coil patterns being connected with each other at a part where the coil patterns overlap with each other.

Abstract: An electronic component device testing apparatus includes first contacts arrayed so that first ends of the first contacts positionally correspond to electrode pads arrayed on a surface of an electronic component device; base electrodes in contact with second ends of the first contacts; and one or more second contacts each being in contact with one of the first contacts at a position which is between the first end and the second end of the one of the first contacts and closer to the first end of the one of the first contacts.

Abstract: This patent specification describes a printed wiring board which includes an insulating board, a wiring pattern, and a resistor pattern. The wiring pattern includes a metallic material and is formed on the insulating board in a process step. The resistor pattern includes the metallic material and is formed on the insulating board at a time together with the wiring pattern in the process step of the wiring pattern.

Abstract: A protection circuit module for a secondary battery including a wiring substrate including two battery-side external connection terminals provided on a top surface thereof, multiple load-side external connection terminals provided on a back surface opposite the top surface, and at least one cutout or through-hole in the wiring substrate; one or more electronic components provided on the wiring substrate; and two metal plates provided respectively on the two battery-side external connection terminals. The at least one cutout or through-hole is provided at a portion of the wiring substrate in which one of the two metal plates is provided, so that a part of the one of the two metal plates is exposed through the cutout or the through-hole when viewed from the back surface of the wiring substrate.

Abstract: A lead terminal bonding method includes the steps of forming a land part on a front surface of a base substrate, the land part including a metal foil; forming a metal plating layer on a surface of the land part, the metal plating layer having a Young's modulus greater than that of the metal foil; and directly bonding a metal plate to the metal plating layer by spot-welding.

Abstract: A printed-circuit board and a circuit unit incorporating the circuit board. The printed-circuit board capable of achieving a suitable contact area of sealing resin includes a metal circuit pattern formed on a substrate, a plurality of mounting electrodes formed on the substrate for electrically connecting at least one electronic component, a resist layer of electrically insulating material disposed over the surface of the substrate having openings in the regions corresponding to the plurality of mounting electrodes, and plurality of external connecting terminals provided on edge portions of the substrate for connecting external devices. The resist layer is preferably formed only on the area surrounding the plurality of mounting electrodes inside a sealing region, the sealing region being resin sealed over the surface of the substrate. A circuit unit is also disclosed, including an electronic device and the above-mentioned printed-circuit board.

Abstract: To cancel a magnetic field in an interconnection pattern of a printed wiring board. A first interconnection pattern 3a is formed on a surface 1a of an insulating substrate 1. A second interconnection pattern 5a is formed on a bottom surface 1b of the insulating substrate 1 so as to be superposed on a meandering part of the first interconnection pattern 3a when viewed from the upper surface side. An end part 5b of the second interconnection pattern 5a is electrically connected to an end part 3d of the first interconnection pattern 3a via through holes 7a. The first interconnection pattern 3a and the second interconnection pattern 5a form a single interconnection line via the through holes 7a. Accordingly, the first interconnection pattern 3a and the second interconnection pattern 5a are 180° different from each other in the direction in which current flows.

Abstract: A printed circuit board comprises a base substrate and an external interconnection terminal provided on the base substrate, wherein external interconnection terminal comprises a land formed on a front surface of the base substrate and a metal plate soldered upon the land via a solder layer, a through-hole being formed in the base substrate such that the through-hole penetrates through the land and through the base substrate, the through-hole being filled with a solder such that the solder in the through-hole extends in continuation to the solder layer connecting the metal plate to the land.

Abstract: A printed circuit board is disclosed that is able to prevent outflow of a potting resin out of a sealing region. The printed circuit board includes a conductive pattern formed on an insulating substrate, an electrode for connecting an electronic part to the conductive pattern, and a stripe-like resin-outflow-prevention dam arranged in a periphery of a resin-sealing region covering the electronic part. An outer side surface and an upper surface of the resin-outflow-prevention dam subtend an acute angle.

Abstract: A printed circuit board comprises a base substrate and an external interconnection terminal provided on the base substrate, wherein external interconnection terminal comprises a land formed on a front surface of the base substrate and a metal plate soldered upon the land via a solder layer, a through-hole being formed in the base substrate such that the through-hole penetrates through the land and through the base substrate, the through-hole being filled with a solder such that the solder in the through-hole extends in continuation to the solder layer connecting the metal plate to the land.

Abstract: An RFID tag comprises a semiconductor chip storing therein information of an object to be discriminated and carrying out radio communication with a reader/writer device; and an antenna coil provided with a magnetic core member and connected electrically to the semiconductor chip. The semiconductor chip and the magnetic core member are wrapped by an insulation sheet carrying an interconnection pattern connecting a pad of the semiconductor chip and the antenna coil electrically and plural coil patterns on one side thereof. The plural coil patterns includes bar-shaped conductor patterns formed obliquely to the magnetic core member, each of the bar-shaped conductor patterns having an end connected to an end of an adjacent coil pattern, the bar-shaped conductor patterns thereby forming together a spiral coil around the magnetic core member. The coil patterns being connected with each other at a part where the coil patterns overlap with each other.

Abstract: To cancel a magnetic field in an interconnection pattern of a printed wiring board. A first interconnection pattern 3a is formed on a surface 1a of an insulating substrate 1. A second interconnection pattern 5a is formed on a bottom surface 1b of the insulating substrate 1 so as to be superposed on a meandering part of the first interconnection pattern 3a when viewed from the upper surface side. An end part 5b of the second interconnection pattern 5a is electrically connected to an end part 3d of the first interconnection pattern 3a via through holes 7a. The first interconnection pattern 3a and the second interconnection pattern 5a form a single interconnection line via the through holes 7a. Accordingly, the first interconnection pattern 3a and the second interconnection pattern 5a are 180° different from each other in the direction in which current flows.

Abstract: To realize reduction in the size and cost of a protection circuit module for a secondary battery. A protection circuit module 1 for a secondary battery has at least a wiring board 2 having multiple battery-side external terminals 4a and multiple load-side external terminals 20a, and semiconductor components 12 and 14 mounted on the wiring board 2. On the wiring board 2, the battery-side external terminals 4a are disposed on a surface 2a, and the load-side external terminals 20a are disposed on a surface 2b on the opposite side. The semiconductor components 12 and 14 have multiple external connection terminals 12a and 14a arranged on a single plane surface, and are mounted face-down in a bare-chip state on the surface 2a of the wiring board 2.