Abstract: An apparatus includes a plurality of bit-line structures elongating in parallel in a first direction, each of the plurality of bit-line structures having a conductive portion and an insulating portion on the conductive portion; wherein the insulating portion of each of the plurality of bit-line structures includes taper-shaped segments and less taper-shaped segments, which appear alternately along the first direction.

Abstract: Disclosed herein is an apparatus that includes a semiconductor substrate including first and second circuit regions a first trench extending in a first direction and formed between the first and second circuit regions, wherein the first trench includes a first inner wall positioned on the first circuit region side and a second inner van positioned on the second circuit region side, and a plurality of second trenches extending in a second direction different from the first direction and firmed in the first circuit region such that the second trench communicates with the first trench at the first inner wall; and a first insulating film formed on the first and second inner walls such that the second inner wall is covered with the first insulating film without being exposed.

Abstract: A semiconductor device includes a semiconductor body, a first electrode, a control electrode and a control interconnection electrically connected to the control electrode. The first electrode, the control electrode, and the control interconnection are provided on a front surface side of the semiconductor body. The control electrode is shaped as one body in a trench. The control electrode includes a first portion, a second portion, a first end portion and a second end portion that are arranged in a direction along the front surface of the semiconductor body. The first and second portions are positioned between the first and second end portions. The first portion is positioned between the first electrode and the semiconductor body, and the second portion is positioned between the control interconnection and the semiconductor body. The control interconnection crosses the second portion of the control electrode, and is electrically connected thereto.

Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.

Abstract: A semiconductor device includes a semiconductor body, a first electrode, a control electrode and a control interconnection electrically connected to the control electrode. The first electrode, the control electrode, and the control interconnection are provided on a front surface side of the semiconductor body. The control electrode is shaped as one body in a trench. The control electrode includes a first portion, a second portion, a first end portion and a second end portion that are arranged in a direction along the front surface of the semiconductor body. The first and second portions are positioned between the first and second end portions. The first portion is positioned between the first electrode and the semiconductor body, and the second portion is positioned between the control interconnection and the semiconductor body. The control interconnection crosses the second portion of the control electrode, and is electrically connected thereto.

Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.